BIO-RAD 3000Xi - Revision history

Hash: /* System Architecture */

2026-05-25T20:48:52Z

System Architecture

Hash: /* System Architecture */

2026-05-25T20:46:31Z

System Architecture

Hash: /* High-Level Block Diagram */

2026-05-25T20:43:41Z

High-Level Block Diagram

Hash: /* OEM No. 125B - CPU Control Board */

2026-05-25T20:36:07Z

OEM No. 125B - CPU Control Board

Hash: /* OEM No. 125B */

2026-05-25T19:51:59Z

OEM No. 125B

Hash: /* System Architecture */

2026-05-25T19:46:33Z

System Architecture

Hash: /* System Architecture */

2026-05-25T19:45:14Z

System Architecture

Hash: /* OEM No. 127 (A/B) — HV Controller Board */

2026-05-25T18:15:24Z

OEM No. 127 (A/B) — HV Controller Board

Hash: /* OEM No. 127 (A/B) — HV Controller Board */

2026-05-25T18:13:59Z

OEM No. 127 (A/B) — HV Controller Board

Hash: /* Linear Voltage Regulators (Confirmed from photos) */

2026-05-25T17:56:07Z

Linear Voltage Regulators (Confirmed from photos)

@@ Line 38: / Line 38: @@
 !Module!!Function (inferred)!!Status
 |-
-|[[BIO-RAD 3000Xi#OEM No. 125B - CPU Control Board|OEM No. 125B]]||''TBD''||Not yet documented
+|[[BIO-RAD 3000Xi#OEM No. 125B - CPU Control Board|OEM No. 125B]]||CPU Control Board||'''Documented''' below
 |-
-|[[#OEM No. 126C|OEM No. 126C]]||''TBD''||Not yet documented
+|[[#OEM No. 126C|OEM No. 126C]]||User Interface Keyboard/Displays||Not yet documented
 |-
 |[[BIO-RAD 3000Xi#OEM No. 127 .28A.2FB.29 .E2.80.94 HV Controller Board|OEM No. 127A (A/B)]]||HV controller / regulator / telemetry||'''Documented''' below
@@ Line 46: / Line 46: @@
 |[[#OEM No. 128B|OEM No. 128B]]||''TBD''||Not yet documented
 |-
-|[[#OEM No. 130C|OEM No. 130C]]||''TBD''||Not yet documented
+|[[#OEM No. 130C|OEM No. 130C]]||HV Filter/Monitor board||Not yet documented
 |-
 |[[#OEM No. 131A|OEM No. 131A]]||''TBD''||Not yet documented

@@ Line 38: / Line 38: @@
 !Module!!Function (inferred)!!Status
 |-
-|[[#OEM No. 125B|OEM No. 125B]]||''TBD''||Not yet documented
+|[[BIO-RAD 3000Xi#OEM No. 125B - CPU Control Board|OEM No. 125B]]||''TBD''||Not yet documented
 |-
 |[[#OEM No. 126C|OEM No. 126C]]||''TBD''||Not yet documented
@@ Line 59: / Line 59: @@
 ----
-== High-Level Block Diagram ==
+==High-Level Block Diagram==
 <pre>
                   ┌─────────────────────────────────────┐
@@ Line 101: / Line 101: @@
 ----
-== OEM No. 125B - CPU Control Board ==
+==OEM No. 125B - CPU Control Board==
 [[File:BIO-RAD_OEM_NO_125B_Top.jpg|thumb|right|300px|OEM No. 125B — top of board]]
@@ Line 107: / Line 107: @@
 The '''OEM No. 125B''' is the system CPU / control board — referenced in the [[#High-Level Block Diagram|block diagram]]. It runs the instrument firmware, drives the [[#OEM No. 126C|OEM No. 126C]] front-panel board (LCD, LED readouts, keypad) over J-2, and commands the [[#OEM No. 127 (A/B) — HV Controller Board|OEM No. 127]] HV controller over J-3 — sending the 12-bit DAC setpoint and reading back the voltage / current PWM telemetry and circuit-status lines. Run parameters are retained in battery-backed RAM. The board is built around the Motorola 6800-family set (MC6809 CPU, MC6821 PIA, dual MC6840 timers). Date codes place it at 1988; the EPROM is hand-labelled firmware "Xi 4.0".
-=== Active Components ===
+===Active Components===
 {| class="wikitable"
-! Ref !! Part !! Function
+!Ref!!Part!!Function
 |-
-| '''M1''' || Motorola MC6809P || 8-bit microprocessor — main CPU
+|'''M1'''||Motorola MC6809P||8-bit microprocessor — main CPU
 |-
-| '''M6''' || Motorola MC6821P || Peripheral Interface Adapter (PIA), two 8-bit parallel ports — front-panel keypad/display I/O and the J-3 handshake to the 127 board (HV-enable, DAC clock/data/strobe, circuit open/shorted/unknown status)
+|'''M6'''||Motorola MC6821P||Peripheral Interface Adapter (PIA), two 8-bit parallel ports — front-panel keypad/display I/O and the J-3 handshake to the 127 board (HV-enable, DAC clock/data/strobe, circuit open/shorted/unknown status)
 |-
-| '''M4, M5''' || Motorola MC6840P (×2) || Programmable Timer Module, three 16-bit counter/timers each — volt-hour / run timing and capture of the voltage- and current-PWM telemetry from the 127 board
+|'''M4, M5'''||Motorola MC6840P (×2)||Programmable Timer Module, three 16-bit counter/timers each — volt-hour / run timing and capture of the voltage- and current-PWM telemetry from the 127 board
 |-
-| '''M2''' || Hitachi HN27256G-25 || 256 Kbit (32K×8) UV-EPROM — program store; windowed, V<sub>PP</sub> 12.5 V, hand-labelled "Xi 4.0"
+|'''M2'''||Hitachi HN27256G-25||256 Kbit (32K×8) UV-EPROM — program store; windowed, V<sub>PP</sub> 12.5 V, hand-labelled "Xi 4.0"
 |-
-| '''M3''' || Toshiba TC5564APL-15 || 64 Kbit (8K×8) static RAM — work / settings RAM, battery-backed by BAT1
+|'''M3'''||Toshiba TC5564APL-15||64 Kbit (8K×8) static RAM — work / settings RAM, battery-backed by BAT1
 |-
-| '''M7''' || Signetics CK2605 || FPGA — system glue logic (address decode / control sequencing)
+|'''M7'''||Signetics CK2605||FPGA — system glue logic (address decode / control sequencing)
 |-
-| '''M11''' || Hitachi HD74LS640P || Octal inverting bus transceiver — data-bus buffer
+|'''M11'''||Hitachi HD74LS640P||Octal inverting bus transceiver — data-bus buffer
 |-
-| '''M12''' || Motorola MC74HCT240 || Octal inverting 3-state buffer/line driver — address / control buffer
+|'''M12'''||Motorola MC74HCT240||Octal inverting 3-state buffer/line driver — address / control buffer
 |-
-| '''M8''' || Toshiba 74HC138AP || 3-to-8 line decoder — address decode / chip selects
+|'''M8'''||Toshiba 74HC138AP||3-to-8 line decoder — address decode / chip selects
 |-
-| '''M9''' || Toshiba TC74HC4020P || 14-stage binary ripple counter — clock division / timing
+|'''M9'''||Toshiba TC74HC4020P||14-stage binary ripple counter — clock division / timing
 |-
-| '''M14, M15''' || Toshiba TC74HC132P (×2) || Quad 2-input NAND Schmitt trigger
+|'''M14, M15'''||Toshiba TC74HC132P (×2)||Quad 2-input NAND Schmitt trigger
 |-
-| '''M18, M22''' || Toshiba 74HC00AP (×2) || Quad 2-input NAND gate
+|'''M18, M22'''||Toshiba 74HC00AP (×2)||Quad 2-input NAND gate
 |-
-| '''M16''' || Toshiba 74HC08AP || Quad 2-input AND gate
+|'''M16'''||Toshiba 74HC08AP||Quad 2-input AND gate
 |-
-| '''M17''' || Toshiba 74HC14AP || Hex Schmitt-trigger inverter
+|'''M17'''||Toshiba 74HC14AP||Hex Schmitt-trigger inverter
 |-
-| '''M10''' || Seiko S-8054ALR || Voltage detector — power-on reset / low-voltage supervisor
+|'''M10'''||Seiko S-8054ALR||Voltage detector — power-on reset / low-voltage supervisor
 |-
-| '''M21''' || National Semiconductor LM358N || Dual op-amp — analog signal conditioning / comparator
+|'''M21'''||National Semiconductor LM358N||Dual op-amp — analog signal conditioning / comparator
 |-
-| '''M20''' || Maxim ICL7660CPA || Switched-capacitor voltage converter — generates the −5 V rail (TP3) from +5 V
+|'''M20'''||Maxim ICL7660CPA||Switched-capacitor voltage converter — generates the −5 V rail (TP3) from +5 V
 |-
-| '''M19''' || Toshiba TDG2002P (TD62002) || 7-channel Darlington sink driver array — drives buzzer / indicators / low-current loads
+|'''M19'''||Toshiba TDG2002P (TD62002)||7-channel Darlington sink driver array — drives buzzer / indicators / low-current loads
 |}
-=== Clock & Configuration ===
+===Clock & Configuration===
-* '''X1''' — 4 MHz crystal (MC6809 ÷4 → 1 MHz E/Q bus clock), with C1/C2 loading trimmers
+*'''X1''' — 4 MHz crystal (MC6809 ÷4 → 1 MHz E/Q bus clock), with C1/C2 loading trimmers
-* '''JMP1''' — 3-position configuration jumper
+*'''JMP1''' — 3-position configuration jumper
-* '''BAT1''' — lithium coin cell, backup for the TC5564 SRAM
+*'''BAT1''' — lithium coin cell, backup for the TC5564 SRAM
-* '''M13''' — unpopulated 8-pin position
+*'''M13''' — unpopulated 8-pin position
-=== Connectors ===
+===Connectors===
 {| class="wikitable"
-! Connector !! Function
+!Connector!!Function
 |-
-| '''J-1''' || +5 V power input to the board
+|'''J-1'''||+5 V power input to the board
 |-
-| '''J-2''' || Front-panel board ([[#OEM No. 126C|OEM No. 126C]]) — LCD display, LED readouts, keypad (40-pin ribbon)
+|'''J-2'''||Front-panel board ([[#OEM No. 126C|OEM No. 126C]]) — LCD display, LED readouts, keypad (40-pin ribbon)
 |-
-| '''J-3''' || HV control board ([[#OEM No. 127 (A/B) — HV Controller Board|OEM No. 127]]) — maps pin-for-pin to the 127 board's [[#J-16 Data, Status and Telemetry|J-16]]: DAC setpoint out, voltage/current PWM telemetry in, circuit open/shorted/unknown status
+|'''J-3'''||HV control board ([[#OEM No. 127 (A/B) — HV Controller Board|OEM No. 127]]) — maps pin-for-pin to the 127 board's [[#J-16 Data, Status and Telemetry|J-16]]: DAC setpoint out, voltage/current PWM telemetry in, circuit open/shorted/unknown status
 |-
-| '''J-4, J-5''' || Small I/O harnesses (3-pin) — function TBD
+|'''J-4, J-5'''||Small I/O harnesses (3-pin) — function TBD
 |}
-=== Other ===
+===Other===
-* '''BZ1''' — muRata piezo buzzer (audible alarm / key-click)
+*'''BZ1''' — muRata piezo buzzer (audible alarm / key-click)
-* '''Q1–Q5''' transistors, '''D1–D13''' diodes — discrete interface / level shifting
+*'''Q1–Q5''' transistors, '''D1–D13''' diodes — discrete interface / level shifting
-* Test points '''TP1–TP7''', '''+5 V''', '''−5 V''' (from ICL7660), '''GND'''
+*Test points '''TP1–TP7''', '''+5 V''', '''−5 V''' (from ICL7660), '''GND'''
-* An unpopulated 20-pin DIP position sits between M3 and M11
+*An unpopulated 20-pin DIP position sits between M3 and M11
-=== Reverse-Engineering Notes ===
+===Reverse-Engineering Notes===
-# The MC6809 + MC6821 + dual MC6840 set is a textbook Motorola control core. The two PTMs are well-suited to ''measuring'' the voltage-PWM and current-PWM the 127 board returns over J-3 (gate / capture), and to generating the volt-hour and timed-run intervals for the four operating modes.
+#The MC6809 + MC6821 + dual MC6840 set is a textbook Motorola control core. The two PTMs are well-suited to ''measuring'' the voltage-PWM and current-PWM the 127 board returns over J-3 (gate / capture), and to generating the volt-hour and timed-run intervals for the four operating modes.
-# J-3 is wired pin-for-pin to the 127 board's J-16, so the 125B PIA directly drives that interface: HV-enable, DAC clock / data / strobe out; circuit open / shorted / unknown status in. The keypad scan / display strobes go to the front panel on J-2.
+#J-3 is wired pin-for-pin to the 127 board's J-16, so the 125B PIA directly drives that interface: HV-enable, DAC clock / data / strobe out; circuit open / shorted / unknown status in. The keypad scan / display strobes go to the front panel on J-2.
-# The Signetics CK2605 FPGA (M7) handles glue logic — address decoding and control sequencing — alongside the discrete 74HC138 / HC00 / HC132 gates.
+#The Signetics CK2605 FPGA (M7) handles glue logic — address decoding and control sequencing — alongside the discrete 74HC138 / HC00 / HC132 gates.
-# The S-8054 voltage detector (M10) provides power-on reset and brown-out supervision, gating the CPU and protecting the battery-backed SRAM during power transitions.
+#The S-8054 voltage detector (M10) provides power-on reset and brown-out supervision, gating the CPU and protecting the battery-backed SRAM during power transitions.
-# The ICL7660 makes a local −5 V rail for the analog / op-amp section rather than relying on the 127 board's ±15 V.
+#The ICL7660 makes a local −5 V rail for the analog / op-amp section rather than relying on the 127 board's ±15 V.
-=== Items Still to Confirm ===
+===Items Still to Confirm===
-* Identify the J-4 / J-5 harnesses
+*Identify the J-4 / J-5 harnesses
-* Dump the CK2605 (M7) configuration / determine its logic role
+*Dump the CK2605 (M7) configuration / determine its logic role
-* Determine J2 pinout to front panel board
+*Determine J2 pinout to front panel board
 ==OEM No. 127 (A/B) — HV Controller Board==

@@ Line 59: / Line 59: @@
 ----
-==High-Level Block Diagram==
+== High-Level Block Diagram ==
 <pre>
                   ┌─────────────────────────────────────┐
-                  │  Front-Panel Microprocessor (μC)    │
+                  │  Front-Panel Board (OEM No. 126C)   │
-                  │  (LCD, keypad, programming logic)   │
+                  │  LCD + driver, keypad, LED displays │
                   └────────────────┬────────────────────┘
-                                   │ ribbon (J-16)
+                                   │ ribbon (J7 ↔ J-2)
                                    ▼
     ┌─────────────────────────────────────────────────────────┐
@@ Line 73: / Line 80: @@
     │  │ Opto-iso.  │─▶|  TC4584    │─▶│ AD7543 12-bit   │   │
     │  │ rcv (TLP)  │   │  Schmitt   │  │ serial-in DAC   │   │
-    │  └────────────┘   └────────────┘  └────────┬────────┘   │
+    │  └────────────┘   └────────────┘  └───────┬─────────┘   │
     │                                           ▼             │
     │                                ┌────────────────────┐   │
@@ Line 80: / Line 87: @@
     │                                └─────────┬──────────┘   │
     │                                          ▲              │
-    │  ┌────────────┐  ┌────────────┐  ┌───────┴────────┐     │
+    │  ┌────────────┐  ┌────────────┐   ┌──────┴─────────┐    │
-    │  │ Opto-iso.  │◀─│ AD654 V/F  │◀─│ LF353 / LM358  │◀────┼── HV feedback
+    │  │ Opto-iso.  │◀─│ AD654 V/F  │◀─│ LF353 / LM358  │◀──┼── HV feedback
-    │  │ tx  (TLP)  │  │ converter  │  │ signal cond.   │     │   (J-13/J-14)
+    │  │ tx  (TLP)  │  │ converter  │   │ signal cond.   │    │   (J-13/J-14)
-    │  └────────────┘  └────────────┘  └────────────────┘     │
+    │  └────────────┘  └────────────┘   └────────────────┘    │
     │                                                         │
-    │  Protection: LM358 comp. → TC4013 latch → IR3M02 SD ◀───┼── J-15
+    │  Protection: LM358 comp. → TC4013 latch → IR3M02 SD ◀──┼── J-15
     └─────────────────────────────────────────────────────────┘
                                    │
@@ Line 92: / Line 99: @@
                transformer → rectifier/multiplier → output jacks)
 </pre>
 ----

@@ Line 95: / Line 95: @@
 ----
-==OEM No. 125B - CPU Control Board==
+== OEM No. 125B - CPU Control Board ==
-To be filled in.
+[[File:BIO-RAD_OEM_NO_125B_Top.jpg|thumb|right|300px|OEM No. 125B — top of board]]
-<br />
+The '''OEM No. 125B''' is the system CPU / control board — referenced in the [[#High-Level Block Diagram|block diagram]]. It runs the instrument firmware, drives the [[#OEM No. 126C|OEM No. 126C]] front-panel board (LCD, LED readouts, keypad) over J-2, and commands the [[#OEM No. 127 (A/B) — HV Controller Board|OEM No. 127]] HV controller over J-3 — sending the 12-bit DAC setpoint and reading back the voltage / current PWM telemetry and circuit-status lines. Run parameters are retained in battery-backed RAM. The board is built around the Motorola 6800-family set (MC6809 CPU, MC6821 PIA, dual MC6840 timers). Date codes place it at 1988; the EPROM is hand-labelled firmware "Xi 4.0".
 ==OEM No. 127 (A/B) — HV Controller Board==

@@ Line 94: / Line 94: @@
 ----
 ==OEM No. 127 (A/B) — HV Controller Board==
@@ Line 381: / Line 387: @@
 ----
 ==OEM No. 126C==

@@ Line 42: / Line 42: @@
 |[[#OEM No. 126C|OEM No. 126C]]||''TBD''||Not yet documented
 |-
-|[[#OEM No. 127A — HV Controller Board|OEM No. 127A]]||HV controller / regulator / telemetry||'''Documented''' below
+|[[#OEM No. 127A — HV Controller Board|OEM No. 127A (A/B)]]||HV controller / regulator / telemetry||'''Documented''' below
 |-
 |[[#OEM No. 128B|OEM No. 128B]]||''TBD''||Not yet documented

@@ Line 98: / Line 98: @@
 This is the analog/digital control board that bridges the front-panel microprocessor and the high-voltage power module. It accepts a digital setpoint from the μC, generates two PWM drive signals to control the HV switcher, and reports back the actual HV and HC values via a frequency-isolated telemetry path. It also handles fault detection and shutdown latching.<gallery mode="slideshow">
 File:BIO-RAD OEM NO 127A Top.jpg|'''127A''' - Top of board, J-16 and optocouplers in bottom left
-File:BIO-RAD OEM NO 127A Bottom.jpg|'''127B''' - Bottom of board, cutout under optocouplers in top left for high voltage isolation
+File:BIO-RAD OEM NO 127A Bottom.jpg|'''127A''' - Bottom of board, cutout under optocouplers in top left for high voltage isolation
 File:BIO-RAD OEM NO 127B Top.jpg|'''127B''' - Top of board, J-16 and optocouplers in top right
 File:BIO-RAD OEM NO 127B Bottom.jpg|'''127B''' - Bottom of board, cutout under optocouplers in top left for high voltage isolation

@@ Line 97: / Line 97: @@
 ==OEM No. 127 (A/B) — HV Controller Board==
 This is the analog/digital control board that bridges the front-panel microprocessor and the high-voltage power module. It accepts a digital setpoint from the μC, generates two PWM drive signals to control the HV switcher, and reports back the actual HV and HC values via a frequency-isolated telemetry path. It also handles fault detection and shutdown latching.<gallery mode="slideshow">
-File:BIO-RAD OEM NO 127B Top.jpg|Top of board, J-16 and optocouplers in top right
+File:BIO-RAD OEM NO 127A Top.jpg|'''127A''' - Top of board, J-16 and optocouplers in bottom left
-File:BIO-RAD OEM NO 127B Bottom.jpg|Bottom of board, cutout under optocouplers in top left for high voltage isolation
+File:BIO-RAD OEM NO 127A Bottom.jpg|'''127B''' - Bottom of board, cutout under optocouplers in top left for high voltage isolation
 </gallery>
 ===Connector Map===

@@ Line 331: / Line 331: @@
 |-
 |'''REG3'''||7915||'''−15 V''' analog rail
-|[https://www.ti.com/lit/ds/symlink/lm7900.pdf 79xx PDF (TI)]
+|[https://www.ti.com/lit/ds/symlink/lm79.pdf 79xx PDF (TI)]
 |-
 |'''REG4'''||7812||'''+12 V''' rail||[https://www.ti.com/lit/ds/symlink/lm340.pdf 78M PDF (TI)]