ATSAM4C32: Difference between revisions

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===Locking Mechanism===

The SAM4C32 makes use of general-purpose non-volatile memory (GPNVM) bits to control locking ~~(security GPNVM bit 0)~~, boot mode and memory plane selection as seen below.~~<br />~~[[File:ATSAM4C32 Table 8-3.png|alt=]]

The SAM4C32 makes use of general-purpose non-volatile memory (GPNVM) bits to control locking, boot mode and memory plane selection as seen below.[[File:ATSAM4C32 Table 8-3.png|alt=]]'''''Below is extracted from Microchip datasheet DS60001717B.'''''

==== Security Bit ====

The SAM4C features a security bit based on a specific General-purpose NVM bit (GPNVM bit 0). When the security is enabled, any access to the Flash, SRAM, core registers and internal peripherals, either through the SW-DP/JTAG-DP interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash.

This security bit can only be enabled through the command “Set General-purpose NVM Bit 0” of the EEFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated, all accesses to the Flash, SRAM, Core registers, Internal Peripherals are permitted.

==== SAM-BA Boot ====

The SAM-BA Boot is a default Boot Program for the master processor (CM4P0) which provides an easy way to program in-situ the onchip Flash memory. The SAM-BA Boot Assistant supports serial communication via the UART0 or USB Port for the SAM4C32.

The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).

The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0.

===Reset vs Power Cycle===

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 ===Locking Mechanism===
-The SAM4C32 makes use of general-purpose non-volatile memory (GPNVM) bits to control locking (security GPNVM bit 0), boot mode and memory plane selection as seen below.<br />[[File:ATSAM4C32 Table 8-3.png|alt=]]
+The SAM4C32 makes use of general-purpose non-volatile memory (GPNVM) bits to control locking, boot mode and memory plane selection as seen below.[[File:ATSAM4C32 Table 8-3.png|alt=]]'''''Below is extracted from Microchip datasheet DS60001717B.'''''
+==== Security Bit ====
+The SAM4C features a security bit based on a specific General-purpose NVM bit (GPNVM bit 0). When the security is enabled, any access to the Flash, SRAM, core registers and internal peripherals, either through the SW-DP/JTAG-DP interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash.
+This security bit can only be enabled through the command “Set General-purpose NVM Bit 0” of the EEFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated, all accesses to the Flash, SRAM, Core registers, Internal Peripherals are permitted.
+==== SAM-BA Boot ====
+The SAM-BA Boot is a default Boot Program for the master processor (CM4P0) which provides an easy way to program in-situ the onchip Flash memory. The SAM-BA Boot Assistant supports serial communication via the UART0 or USB Port for the SAM4C32.
+The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
+The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0.
 ===Reset vs Power Cycle===