Changes

Here Below are some general pinout notes on the DIF-AT RBUS and Digital Audio flow, and the connections to the Alesis Chip (which seems to do all the heavy lifting as regards audio and timing)

All audio formats go directly into the Alesis chip, and it handles so much, audio formats, inputs, - BREQ bus arbitration, WE to Flash, CE with mux to Flash, that it must be an ASIC. Any thoughts on this, or anything else here, are most welcome.

The Xilinx chip is handling RBUS signals only, after they leave the Alesis chip, they go into the Xilinx CPLD, and leave the DIF AT via an inverter. I will inspect the signals before and after the Xilinx chip cpld to see how it is processing the data after the Alesis chip.