BIO-RAD 3000Xi: Difference between revisions

(27 intermediate revisions by the same user not shown)

Line 38:

!Module!!Function (inferred)!!Status

|-

|[[#OEM No. 125B|OEM No. 125B]]||''~~TBD~~''~~||Not yet documented~~

|[[BIO-RAD 3000Xi#OEM No. 125B - CPU Control Board|OEM No. 125B]]||CPU Control Board||'''Documented''' below

|-

|[[#OEM No. 126C|OEM No. 126C]]||~~''TBD''~~||Not yet documented

|[[#OEM No. 126C|OEM No. 126C]]||User Interface Keyboard/Displays||Not yet documented

|-

|[[#OEM No. ~~127A —~~ HV Controller Board|OEM No. 127A]]||HV controller / regulator / telemetry||'''Documented''' below

|[[BIO-RAD 3000Xi#OEM No. 127 .28A.2FB.29 .E2.80.94 HV Controller Board|OEM No. 127A (A/B)]]||HV controller / regulator / telemetry||'''Documented''' below

|-

|[[#OEM No. 128B|OEM No. 128B]]||''TBD''||Not yet documented

|-

|[[#OEM No. 130C|OEM No. 130C]]||~~''TBD''~~||Not yet documented

|[[#OEM No. 130C|OEM No. 130C]]||HV Filter/Monitor board||Not yet documented

|-

|[[#OEM No. 131A|OEM No. 131A]]||''TBD''||Not yet documented

Line 60:

==High-Level Block Diagram==

<pre>

┌─────────────────────────────────────┐

│ Front-Panel ~~Microprocessor~~ (μC) │

│ Front-Panel Board (OEM No. 126C) │

│ (LCD, keypad, ~~programming~~ logic) │

│ LCD + driver, keypad, LED displays │

│ + display/keypad control logic │

└────────────────┬────────────────────┘

│ ribbon (J-16)

│ ribbon (J7 ↔ J-2)

▼

┌─────────────────────────────────────┐

│ OEM No. 125B — CPU Control Board │

│ MC6809 CPU · MC6821 PIA · 2×6840 │

│ EPROM "Xi 4.0" · batt-backed SRAM │

└────────────────┬────────────────────┘

│ ribbon (J-3 ↔ J-16)

▼

┌─────────────────────────────────────────────────────────┐

Line 73:

Line 80:

│ │ Opto-iso. │─▶| TC4584 │─▶│ AD7543 12-bit │ │

│ │ rcv (TLP) │ │ Schmitt │ │ serial-in DAC │ │

│ └────────────┘ └────────────┘ ~~└────────┬────────┘~~ │

│ └────────────┘ └────────────┘ └───────┬─────────┘ │

│ ▼ │

│ ┌────────────────────┐ │

Line 80:

Line 87:

│ └─────────┬──────────┘ │

│ ▲ │

│ ┌────────────┐ ┌────────────┐ ~~┌───────┴────────┐~~ │

│ ┌────────────┐ ┌────────────┐ ┌──────┴─────────┐ │

│ │ Opto-iso. │◀─│ AD654 V/F │◀─│ LF353 / LM358 ~~│◀────┼──~~ HV feedback

│ │ Opto-iso. │◀─│ AD654 V/F │◀─│ LF353 / LM358 │◀──┼── HV feedback

│ │ tx (TLP) │ │ converter │ │ signal cond. │ │ (J-13/J-14)

│ └────────────┘ └────────────┘ └────────────────┘ │

│ │

│ Protection: LM358 comp. → TC4013 latch → IR3M02 SD ~~◀───┼──~~ J-15

│ Protection: LM358 comp. → TC4013 latch → IR3M02 SD ◀──┼── J-15

└─────────────────────────────────────────────────────────┘

│

Line 92:

Line 99:

transformer → rectifier/multiplier → output jacks)

</pre>

----

==OEM No. 125B - CPU Control Board==

[[File:BIO-RAD_OEM_NO_125B_Top.jpg|thumb|right|300px|OEM No. 125B — top of board]]

The '''OEM No. 125B''' is the system CPU / control board — referenced in the [[#High-Level Block Diagram|block diagram]]. It runs the instrument firmware, drives the [[#OEM No. 126C|OEM No. 126C]] front-panel board (LCD, LED readouts, keypad) over J-2, and commands the [[#OEM No. 127 (A/B) — HV Controller Board|OEM No. 127]] HV controller over J-3 — sending the 12-bit DAC setpoint and reading back the voltage / current PWM telemetry and circuit-status lines. Run parameters are retained in battery-backed RAM. The board is built around the Motorola 6800-family set (MC6809 CPU, MC6821 PIA, dual MC6840 timers). Date codes place it at 1988; the EPROM is hand-labelled firmware "Xi 4.0".

===Active Components===

{| class="wikitable"

!Ref!!Part!!Function

|-

|'''M1'''||Motorola MC6809P||8-bit microprocessor — main CPU

|-

|'''M6'''||Motorola MC6821P||Peripheral Interface Adapter (PIA), two 8-bit parallel ports — front-panel keypad/display I/O and the J-3 handshake to the 127 board (HV-enable, DAC clock/data/strobe, circuit open/shorted/unknown status)

|-

|'''M4, M5'''||Motorola MC6840P (×2)||Programmable Timer Module, three 16-bit counter/timers each — volt-hour / run timing and capture of the voltage- and current-PWM telemetry from the 127 board

|-

|'''M2'''||Hitachi HN27256G-25||256 Kbit (32K×8) UV-EPROM — program store; windowed, VPP 12.5 V, hand-labelled "Xi 4.0"

|-

|'''M3'''||Toshiba TC5564APL-15||64 Kbit (8K×8) static RAM — work / settings RAM, battery-backed by BAT1

|-

|'''M7'''||Signetics CK2605||FPGA — system glue logic (address decode / control sequencing)

|-

|'''M11'''||Hitachi HD74LS640P||Octal inverting bus transceiver — data-bus buffer

|-

|'''M12'''||Motorola MC74HCT240||Octal inverting 3-state buffer/line driver — address / control buffer

|-

|'''M8'''||Toshiba 74HC138AP||3-to-8 line decoder — address decode / chip selects

|-

|'''M9'''||Toshiba TC74HC4020P||14-stage binary ripple counter — clock division / timing

|-

|'''M14, M15'''||Toshiba TC74HC132P (×2)||Quad 2-input NAND Schmitt trigger

|-

|'''M18, M22'''||Toshiba 74HC00AP (×2)||Quad 2-input NAND gate

|-

|'''M16'''||Toshiba 74HC08AP||Quad 2-input AND gate

|-

|'''M17'''||Toshiba 74HC14AP||Hex Schmitt-trigger inverter

|-

|'''M10'''||Seiko S-8054ALR||Voltage detector — power-on reset / low-voltage supervisor

|-

|'''M21'''||National Semiconductor LM358N||Dual op-amp — analog signal conditioning / comparator

|-

|'''M20'''||Maxim ICL7660CPA||Switched-capacitor voltage converter — generates the −5 V rail (TP3) from +5 V

|-

|'''M19'''||Toshiba TDG2002P (TD62002)||7-channel Darlington sink driver array — drives buzzer / indicators / low-current loads

|}

===Clock & Configuration===

*'''X1''' — 4 MHz crystal (MC6809 ÷4 → 1 MHz E/Q bus clock), with C1/C2 loading trimmers

*'''JMP1''' — 3-position configuration jumper

*'''BAT1''' — lithium coin cell, backup for the TC5564 SRAM

*'''M13''' — unpopulated 8-pin position

----

===Connectors===

{| class="wikitable"

!Connector!!Function

|-

|'''J-1'''||+5 V power input to the board

|-

|'''J-2'''||Front-panel board ([[#OEM No. 126C|OEM No. 126C]]) — LCD display, LED readouts, keypad (40-pin ribbon)

|-

|'''J-3'''||HV control board ([[#OEM No. 127 (A/B) — HV Controller Board|OEM No. 127]]) — maps pin-for-pin to the 127 board's [[#J-16 Data, Status and Telemetry|J-16]]: DAC setpoint out, voltage/current PWM telemetry in, circuit open/shorted/unknown status

|-

|'''J-4, J-5'''||Small I/O harnesses (3-pin) — function TBD

|}

===Other===

*'''BZ1''' — muRata piezo buzzer (audible alarm / key-click)

*'''Q1–Q5''' transistors, '''D1–D13''' diodes — discrete interface / level shifting

*Test points '''TP1–TP7''', '''+5 V''', '''−5 V''' (from ICL7660), '''GND'''

*An unpopulated 20-pin DIP position sits between M3 and M11

===Reverse-Engineering Notes===

#The MC6809 + MC6821 + dual MC6840 set is a textbook Motorola control core. The two PTMs are well-suited to ''measuring'' the voltage-PWM and current-PWM the 127 board returns over J-3 (gate / capture), and to generating the volt-hour and timed-run intervals for the four operating modes.

#J-3 is wired pin-for-pin to the 127 board's J-16, so the 125B PIA directly drives that interface: HV-enable, DAC clock / data / strobe out; circuit open / shorted / unknown status in. The keypad scan / display strobes go to the front panel on J-2.

#The Signetics CK2605 FPGA (M7) handles glue logic — address decoding and control sequencing — alongside the discrete 74HC138 / HC00 / HC132 gates.

#The S-8054 voltage detector (M10) provides power-on reset and brown-out supervision, gating the CPU and protecting the battery-backed SRAM during power transitions.

#The ICL7660 makes a local −5 V rail for the analog / op-amp section rather than relying on the 127 board's ±15 V.

==~~OEM No. 127A — HV Controller Board~~==

===Items Still to Confirm===

~~This is~~ the ~~analog~~/~~digital control board that bridges~~ the front-panel microprocessor and the high-voltage power module. It accepts a digital setpoint from the μC, generates two PWM drive signals to control the HV switcher, and reports back the actual HV and HC values via a frequency-isolated telemetry path. It also handles fault detection and shutdown latching.

*Identify the J-4 / J-5 harnesses

*Dump the CK2605 (M7) configuration / determine its logic role

*Determine J2 pinout to front panel board

==OEM No. 127 (A/B) — HV Controller Board==

This is the analog/digital control board that bridges the front-panel microprocessor and the high-voltage power module. It accepts a digital setpoint from the μC, generates two PWM drive signals to control the HV switcher, and reports back the actual HV and HC values via a frequency-isolated telemetry path. It also handles fault detection and shutdown latching.<gallery mode="slideshow">

File:BIO-RAD OEM NO 127A Top.jpg|'''127A''' - Top of board, J-16 and optocouplers in bottom left

File:BIO-RAD OEM NO 127A Bottom.jpg|'''127A''' - Bottom of board, cutout under optocouplers in top left for high voltage isolation

File:BIO-RAD OEM NO 127B Top.jpg|'''127B''' - Top of board, J-16 and optocouplers in top right

File:BIO-RAD OEM NO 127B Bottom.jpg|'''127B''' - Bottom of board, cutout under optocouplers in top left for high voltage isolation

</gallery>

===Connector Map===

Line 115:

Line 214:

|}

=== J-12 Power-Input Topology ===

===J-12 Power-Input Topology===

[[File:BIO-RAD OEM NO 127B Conn J12.jpg|thumb|alt=|none]]

J-12 carries three transformer secondary windings plus a single ground-tie wire. The transformer itself has no center tap or earthed reference — the system ground is '''established on the board''' by bonding the negative DC output of one rectifier to the positive DC output of another, using the lone green wire. This stacks two of the rectified supplies end-to-end to produce the bipolar ±Vunreg rails feeding the ±15 V analog regulators, while the third (blue) winding feeds an independent positive rail for the digital regulators.

==== Stacked Topology ====

====Stacked Topology====

<pre>

Line 148:

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</pre>

==== Wire Color Map ====

====Wire Color Map====

{| class="wikitable"

! Wire !! Conductors !! Function !! Feeds

!Wire!!Conductors!!Function!!Feeds

|-

| '''Yellow''' || pair || Secondary winding #1, feeds bridge rectifier whose "+" output becomes +Vunreg || +15 V regulator (REG2)

|'''Yellow'''||pair||Secondary winding #1, feeds bridge rectifier whose "+" output becomes +Vunreg||+15 V regulator (REG2)

|-

| '''Red''' || pair || Secondary winding #2, feeds bridge rectifier whose "−" output becomes −Vunreg || −15 V regulator (REG1)

|'''Red'''||pair||Secondary winding #2, feeds bridge rectifier whose "−" output becomes −Vunreg||−15 V regulator (REG1)

|-

| '''Green''' || single || Ground bond — ties "−" of the yellow rectifier to "+" of the red rectifier, establishing the 0 V system reference || Analog ground for the entire board

|'''Green'''||single||Ground bond — ties "−" of the yellow rectifier to "+" of the red rectifier, establishing the 0 V system reference||Analog ground for the entire board

|-

| '''Blue''' || pair || Secondary winding #3 (independent), feeds bridge rectifier for the positive logic rail || +12 V (REG3) and +5 V (REG4) regulators

|'''Blue'''||pair||Secondary winding #3 (independent), feeds bridge rectifier for the positive logic rail||+12 V (REG3) and +5 V (REG4) regulators

|}

==== Notes on the Topology ====

====Notes on the Topology====

*The transformer has '''three independent floating secondaries''' — no center tap is brought out. The bipolar ±15 V rail pair is synthesized on the board by stacking two single-ended supplies via the green ground-tie wire.

*The green wire is a '''current-carrying ground return''', not just a reference. The imbalance current between the +15 V and −15 V loads flows through it back to the rectifier diodes, so it should be a reasonable gauge and routed for low loop inductance. Lifting it during service work will collapse the entire analog ground reference of the board.

*Because the "+" pin of the red bridge rectifier is bonded to ground, the red supply's '''negative''' DC output is the rail that goes down to the −15 V regulator. This is normal for a stacked topology but can be confusing if you expect the rectifier "+" pin to be the rail output.

*Keeping the digital +5 V / +12 V supply on its own winding (blue) isolates digital switching noise from the ±15 V analog rails, which carry the precision references for the AD7543 DAC and the AD654 V/F converters.

* The transformer has '''three independent floating secondaries''' — no center tap is brought out. ~~The bipolar ±15 V rail pair is synthesized~~ on the ~~board~~ by ~~stacking two single~~-~~ended supplies via~~ the ~~green ground-tie wire~~.

===J-16 Data, Status and Telemetry===

* The green wire is a '''current-carrying ground return''', not just a reference. ~~The imbalance~~ current ~~between the +15 V~~ and ~~−15 V loads flows through it back~~ to ~~the rectifier diodes~~, ~~so it should be~~ a ~~reasonable gauge and routed for low loop inductance. Lifting it during service work will collapse the entire analog~~ ground ~~reference of~~ the ~~board~~.

[[File:BIO-RAD OEM NO 127B Conn J16.jpg|none|thumb]]

* Because the "+" pin of the red bridge rectifier is bonded to ground, the red supply's '''negative''' DC output is the rail that goes ~~down~~ to the ~~−15 V regulator. This~~ is ~~normal for a stacked topology but can be confusing if you expect the rectifier "+" pin to be the rail output.~~

J-16 carries four data lines to an on-board [https://wiki.recessim.com/w/images/f/fc/AD7543.PDF AD7543] Digital to Analog Converter (DAC) which selects the voltage generated by the power supply. 0 - 4095 is the valid range to set ~20V to 3000V in 0.7V increments. It also has PWM outputs for voltage and current to monitor actual values and three additional I/O lines to signal Circuit Open, Circuit Shorted and one Circuit Unknown, possibly to signal a ground fault condition per the user manual. This connector goes straight to optocouplers so the control side is isolated from the high voltage side.

* Keeping the digital +5 V / +12 V supply on its own winding (blue) isolates digital switching noise from the ~~±15 V analog rails, which carry the precision references for the AD7543 DAC and the AD654 V/F converters~~.

====Pin Definitions====

{| class="wikitable"

|+J-16 Pinout

!Position

!Function

!Direction

!To IC pin

!Notes

|-

|1

| +5V

|Input

|PC1-1,3,5,7

|Supplied by the logic board to the Optocoupler drivers used to send data to the DAC

|-

|2

|Voltage PWM

|Output

|PC2-16

|PWM output corresponding to voltage level

|-

|3

|Current PWM

|Output

|PC2-14

|PWM output corresponding to current draw

|-

|4

|Circuit Unknown

|Output

|PC3-4

|Possibly a ground fault indicator

|-

|5

|Circuit Open

|Output

|PC2-12

|Indicates if a load is connected to the High Voltage output

|-

|6

|Circuit Shorted

|Output

|PC2-10

|Indicates if the High Voltage output is shorted

|-

|7

|HV Enable

|Input

|PC1-8

|Active Low - Set low to enable HV output control by DAC, set high to disable HV supply

|-

|8

|DAC Clock

|Input

|PC1-6

|Active Low - 12 clock cycles

|-

|9

|DAC Data

|Input

|PC1-4

|Active Low - Data MSB

|-

|10

|DAC Strobe

|Input

|PC1-2

|Active High - Strobe signal at the end of the data load

|-

|11, 12

|GND

|Input

|PC3-3

PC2-9,11,13,15

|Ground supplied by logic board to Optocoupler receivers used to communicate back to logic board

|}

====Timing Information====

File:BIO-RAD 3000Xi DAC Data Capture.png

File:BIO-RAD 3000Xi DAC Data Capture - Enable to Clock.png|HV Enable low to start of data

File:BIO-RAD 3000Xi DAC Data Capture - Clock Timing.png|Clock signal timing

File:BIO-RAD 3000Xi DAC Data Capture - Data Timing.png|Data signal timing, centered within clock

File:BIO-RAD 3000Xi DAC Data Capture - Clock to Strobe.png|End of clock to strobe timing

</gallery>

===Active Components===

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!Part Number!!Marking!!Package!!Function!!Datasheet

|-

|'''Analog Devices AD7543JN'''||"AD7543JN"||16-DIP||CMOS 12-bit '''serial-input''' monolithic multiplying DAC, R-2R ladder. Has an internal 12-bit serial-in parallel-out shift register (Register A) plus a separate 12-bit DAC input register (Register B), so the chip accepts serial setpoint data directly from the μC — no external shift register required. The two-register architecture lets the μC clock in a new code while the DAC continues to hold the previous value, then transfer it cleanly with a LOAD pulse. Asynchronous CLEAR input zeroes Register B for safe initialization. With 12-bit resolution this gives '''~0.7 V resolution at 3000 V full-scale''' — consistent with Bio-Rad's published 1 V step granularity. The "multiplying" feature is convenient because VREF can be scaled by an external precision reference for absolute-voltage trim.||[https://www.analog.com/en/products/ad7543.html AD7543 product page] · [https://~~www~~.~~alldatasheet~~.com/~~datasheet-pdf~~/~~pdf~~/~~48235~~/AD/AD7543.~~html~~ PDF]

|'''Analog Devices AD7543JN'''||"AD7543JN"||16-DIP||CMOS 12-bit '''serial-input''' monolithic multiplying DAC, R-2R ladder. Has an internal 12-bit serial-in parallel-out shift register (Register A) plus a separate 12-bit DAC input register (Register B), so the chip accepts serial setpoint data directly from the μC — no external shift register required. The two-register architecture lets the μC clock in a new code while the DAC continues to hold the previous value, then transfer it cleanly with a LOAD pulse. Asynchronous CLEAR input zeroes Register B for safe initialization. With 12-bit resolution this gives '''~0.7 V resolution at 3000 V full-scale''' — consistent with Bio-Rad's published 1 V step granularity. The "multiplying" feature is convenient because VREF can be scaled by an external precision reference for absolute-voltage trim.||[https://www.analog.com/en/products/ad7543.html AD7543 product page] · [https://wiki.recessim.com/w/images/f/fc/AD7543.PDF PDF]

|}

Line 224:

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!Part Number!!Marking!!Package!!Function!!Datasheet

|-

|'''TLP621-4''' (×2)||"T8K TLP621-4 GB"||16-DIP||Quad transistor-output optocoupler, 5 kVrms isolation, CTR 100–600 %. Together they provide 8 isolated digital channels — sufficient for the AD7543's serial interface (SRI data, STB clock, LD load, CLR clear), master enable, fault status, plus the two AD654 frequency-out telemetry channels.||[~~https~~:~~//uk.farnell~~.~~com/toshiba/tlp621-4-gb/optocoupler-quad-5kv-transtr-o/dp/1225839 Farnell page~~]

|'''TLP621-4''' (×2)||"T8K TLP621-4 GB"||16-DIP||Quad transistor-output optocoupler, 5 kVrms isolation, CTR 100–600 %. Together they provide 8 isolated digital channels — sufficient for the AD7543's serial interface (SRI data, STB clock, LD load, CLR clear), master enable, fault status, plus the two AD654 frequency-out telemetry channels.||[[:File:TLP621 datasheet.pdf|Datasheet]]

|-

|'''TLP621''' (×1)||"T7K P621"||4-DIP||Single-channel version. Probably an additional status / interlock line, or a high-priority signal kept on its own isolation domain.||[~~https~~:~~//toshiba.semicon-storage.com/us/semiconductor/product/isolators-solid-state-relays~~.~~html Toshiba family~~]

|'''TLP621''' (×1)||"T7K P621"||4-DIP||Single-channel version. Probably an additional status / interlock line, or a high-priority signal kept on its own isolation domain.||[[:File:TLP621 datasheet.pdf|Datasheet]]

|}

Line 232:

Line 422:

{| class="wikitable"

!Position!!Part Number~~!!Marking~~!!Output!!Datasheet

!Position!!Part Number!!Output!!Datasheet

|-

|'''REG1'''||~~Fairchild '''μA79M15A''' (Korea)||"μA79M15A UC871x KOREA"~~||'''~~−15 V~~''' ~~analog rail~~||[https://www.ti.com/lit/ds/symlink/~~lm7900~~.pdf ~~79xx~~ PDF (TI)]

|'''REG1'''||7805||'''+5V''' Digital Rail||[https://www.ti.com/lit/ds/symlink/lm340.pdf LM340 PDF (TI)]

|-

|'''REG2'''||~~Fairchild '''μA 78M15''' (Korea)||"μA 78M15 UC8704 KOREA"~~||'''+15 V''' analog rail||[https://www.ti.com/lit/ds/symlink/lm340.pdf 78xx PDF (TI)]

|'''REG2'''||7815||'''+15 V''' analog rail||[https://www.ti.com/lit/ds/symlink/lm340.pdf 78xx PDF (TI)]

|-

|'''REG3'~~'' ''(or REG4)~~''||~~National '''LM340T-12'''||"EM340T12 7812 P+" 8730~~||'''~~+12~~ V''' rail||[https://www.ti.com/lit/ds/symlink/~~lm340~~.pdf ~~LM340~~ PDF (TI)]

|'''REG3'''||7915||'''−15 V''' analog rail

|[https://www.ti.com/lit/ds/symlink/lm79.pdf 79xx PDF (TI)]

|-

|'''REG4''' ~~''(or REG3)''||Fairchild '''μA 78M05''' (Korea)~~||~~"μA 78M05 UC8731 KOREA"~~||'''+5 V''' ~~digital~~ rail||[https://www.ti.com/lit/ds/symlink/lm340.pdf 78M PDF (TI)]

|'''REG4'''||7812||'''+12 V''' rail||[https://www.ti.com/lit/ds/symlink/lm340.pdf 78M PDF (TI)]

|}

~~<div style="border-left:4px solid #f0ad4e; background:#fcf8e3; padding:0.5em 1em; margin:1em 0;">~~

~~'''Note:''' REG3 vs REG4 silkscreen position needs confirmation against the TO-220 part numbers — only the REG1/REG2 silkscreen was clearly visible in image 3.~~

~~</div>~~

===Passive Components===

Line 290:

Line 477:

----

~~==OEM No. 125B==~~

~~''Module not yet examined. Photos and reverse-engineering pending.''~~

==OEM No. 126C==

Line 319:

Line 502:

Multi-secondary line-frequency transformer visible at the top-left of the chassis. Has at least three independent floating secondary windings brought out to the OEM No. 127A controller board via J-12:

* '''Yellow pair''' — secondary winding #1, feeds the +15 V analog rail

*'''Yellow pair''' — secondary winding #1, feeds the +15 V analog rail

* '''Red pair''' — secondary winding #2, feeds the −15 V analog rail

*'''Red pair''' — secondary winding #2, feeds the −15 V analog rail

* '''Blue pair''' — secondary winding #3, feeds the +12 V and +5 V digital rails

*'''Blue pair''' — secondary winding #3, feeds the +12 V and +5 V digital rails

A single '''green wire''' also exits the harness at J-12 to bond the rectifier outputs into a stacked bipolar topology (see [[#J-12 Power-Input Topology|J-12 Power-Input Topology]]).

@@ Line 38: / Line 38: @@
 !Module!!Function (inferred)!!Status
 |-
-|[[#OEM No. 125B|OEM No. 125B]]||''TBD''||Not yet documented
+|[[BIO-RAD 3000Xi#OEM No. 125B - CPU Control Board|OEM No. 125B]]||CPU Control Board||'''Documented''' below
 |-
-|[[#OEM No. 126C|OEM No. 126C]]||''TBD''||Not yet documented
+|[[#OEM No. 126C|OEM No. 126C]]||User Interface Keyboard/Displays||Not yet documented
 |-
-|[[#OEM No. 127A — HV Controller Board|OEM No. 127A]]||HV controller / regulator / telemetry||'''Documented''' below
+|[[BIO-RAD 3000Xi#OEM No. 127 .28A.2FB.29 .E2.80.94 HV Controller Board|OEM No. 127A (A/B)]]||HV controller / regulator / telemetry||'''Documented''' below
 |-
 |[[#OEM No. 128B|OEM No. 128B]]||''TBD''||Not yet documented
 |-
-|[[#OEM No. 130C|OEM No. 130C]]||''TBD''||Not yet documented
+|[[#OEM No. 130C|OEM No. 130C]]||HV Filter/Monitor board||Not yet documented
 |-
 |[[#OEM No. 131A|OEM No. 131A]]||''TBD''||Not yet documented
@@ Line 60: / Line 60: @@
 ==High-Level Block Diagram==
 <pre>
                   ┌─────────────────────────────────────┐
-                  │  Front-Panel Microprocessor (μC)    │
+                  │  Front-Panel Board (OEM No. 126C)   │
-                  │  (LCD, keypad, programming logic)   │
+                  │  LCD + driver, keypad, LED displays │
+                 │  + display/keypad control logic     │
                   └────────────────┬────────────────────┘
-                                   │ ribbon (J-16)
+                                   │ ribbon (J7 ↔ J-2)
+                                  ▼
+                 ┌─────────────────────────────────────┐
+                 │  OEM No. 125B — CPU Control Board   │
+                 │  MC6809 CPU · MC6821 PIA · 2×6840   │
+                 │  EPROM "Xi 4.0" · batt-backed SRAM  │
+                 └────────────────┬────────────────────┘
+                                  │ ribbon (J-3 ↔ J-16)
                                    ▼
     ┌─────────────────────────────────────────────────────────┐
@@ Line 73: / Line 80: @@
     │  │ Opto-iso.  │─▶|  TC4584    │─▶│ AD7543 12-bit   │   │
     │  │ rcv (TLP)  │   │  Schmitt   │  │ serial-in DAC   │   │
-    │  └────────────┘   └────────────┘  └────────┬────────┘   │
+    │  └────────────┘   └────────────┘  └───────┬─────────┘   │
     │                                           ▼             │
     │                                ┌────────────────────┐   │
@@ Line 80: / Line 87: @@
     │                                └─────────┬──────────┘   │
     │                                          ▲              │
-    │  ┌────────────┐  ┌────────────┐  ┌───────┴────────┐     │
+    │  ┌────────────┐  ┌────────────┐   ┌──────┴─────────┐    │
-    │  │ Opto-iso.  │◀─│ AD654 V/F  │◀─│ LF353 / LM358  │◀────┼── HV feedback
+    │  │ Opto-iso.  │◀─│ AD654 V/F  │◀─│ LF353 / LM358  │◀──┼── HV feedback
-    │  │ tx  (TLP)  │  │ converter  │  │ signal cond.   │     │   (J-13/J-14)
+    │  │ tx  (TLP)  │  │ converter  │   │ signal cond.   │    │   (J-13/J-14)
-    │  └────────────┘  └────────────┘  └────────────────┘     │
+    │  └────────────┘  └────────────┘   └────────────────┘    │
     │                                                         │
-    │  Protection: LM358 comp. → TC4013 latch → IR3M02 SD ◀───┼── J-15
+    │  Protection: LM358 comp. → TC4013 latch → IR3M02 SD ◀──┼── J-15
     └─────────────────────────────────────────────────────────┘
                                    │
@@ Line 92: / Line 99: @@
                transformer → rectifier/multiplier → output jacks)
 </pre>
+----
+==OEM No. 125B - CPU Control Board==
+[[File:BIO-RAD_OEM_NO_125B_Top.jpg|thumb|right|300px|OEM No. 125B — top of board]]
+The '''OEM No. 125B''' is the system CPU / control board — referenced in the [[#High-Level Block Diagram|block diagram]]. It runs the instrument firmware, drives the [[#OEM No. 126C|OEM No. 126C]] front-panel board (LCD, LED readouts, keypad) over J-2, and commands the [[#OEM No. 127 (A/B) — HV Controller Board|OEM No. 127]] HV controller over J-3 — sending the 12-bit DAC setpoint and reading back the voltage / current PWM telemetry and circuit-status lines. Run parameters are retained in battery-backed RAM. The board is built around the Motorola 6800-family set (MC6809 CPU, MC6821 PIA, dual MC6840 timers). Date codes place it at 1988; the EPROM is hand-labelled firmware "Xi 4.0".
+===Active Components===
+{| class="wikitable"
+!Ref!!Part!!Function
+|-
+|'''M1'''||Motorola MC6809P||8-bit microprocessor — main CPU
+|-
+|'''M6'''||Motorola MC6821P||Peripheral Interface Adapter (PIA), two 8-bit parallel ports — front-panel keypad/display I/O and the J-3 handshake to the 127 board (HV-enable, DAC clock/data/strobe, circuit open/shorted/unknown status)
+|-
+|'''M4, M5'''||Motorola MC6840P (×2)||Programmable Timer Module, three 16-bit counter/timers each — volt-hour / run timing and capture of the voltage- and current-PWM telemetry from the 127 board
+|-
+|'''M2'''||Hitachi HN27256G-25||256 Kbit (32K×8) UV-EPROM — program store; windowed, V<sub>PP</sub> 12.5 V, hand-labelled "Xi 4.0"
+|-
+|'''M3'''||Toshiba TC5564APL-15||64 Kbit (8K×8) static RAM — work / settings RAM, battery-backed by BAT1
+|-
+|'''M7'''||Signetics CK2605||FPGA — system glue logic (address decode / control sequencing)
+|-
+|'''M11'''||Hitachi HD74LS640P||Octal inverting bus transceiver — data-bus buffer
+|-
+|'''M12'''||Motorola MC74HCT240||Octal inverting 3-state buffer/line driver — address / control buffer
+|-
+|'''M8'''||Toshiba 74HC138AP||3-to-8 line decoder — address decode / chip selects
+|-
+|'''M9'''||Toshiba TC74HC4020P||14-stage binary ripple counter — clock division / timing
+|-
+|'''M14, M15'''||Toshiba TC74HC132P (×2)||Quad 2-input NAND Schmitt trigger
+|-
+|'''M18, M22'''||Toshiba 74HC00AP (×2)||Quad 2-input NAND gate
+|-
+|'''M16'''||Toshiba 74HC08AP||Quad 2-input AND gate
+|-
+|'''M17'''||Toshiba 74HC14AP||Hex Schmitt-trigger inverter
+|-
+|'''M10'''||Seiko S-8054ALR||Voltage detector — power-on reset / low-voltage supervisor
+|-
+|'''M21'''||National Semiconductor LM358N||Dual op-amp — analog signal conditioning / comparator
+|-
+|'''M20'''||Maxim ICL7660CPA||Switched-capacitor voltage converter — generates the −5 V rail (TP3) from +5 V
+|-
+|'''M19'''||Toshiba TDG2002P (TD62002)||7-channel Darlington sink driver array — drives buzzer / indicators / low-current loads
+|}
+===Clock & Configuration===
+*'''X1''' — 4 MHz crystal (MC6809 ÷4 → 1 MHz E/Q bus clock), with C1/C2 loading trimmers
+*'''JMP1''' — 3-position configuration jumper
+*'''BAT1''' — lithium coin cell, backup for the TC5564 SRAM
+*'''M13''' — unpopulated 8-pin position
-----
+===Connectors===
+{| class="wikitable"
+!Connector!!Function
+|-
+|'''J-1'''||+5 V power input to the board
+|-
+|'''J-2'''||Front-panel board ([[#OEM No. 126C|OEM No. 126C]]) — LCD display, LED readouts, keypad (40-pin ribbon)
+|-
+|'''J-3'''||HV control board ([[#OEM No. 127 (A/B) — HV Controller Board|OEM No. 127]]) — maps pin-for-pin to the 127 board's [[#J-16 Data, Status and Telemetry|J-16]]: DAC setpoint out, voltage/current PWM telemetry in, circuit open/shorted/unknown status
+|-
+|'''J-4, J-5'''||Small I/O harnesses (3-pin) — function TBD
+|}
+===Other===
+*'''BZ1''' — muRata piezo buzzer (audible alarm / key-click)
+*'''Q1–Q5''' transistors, '''D1–D13''' diodes — discrete interface / level shifting
+*Test points '''TP1–TP7''', '''+5 V''', '''−5 V''' (from ICL7660), '''GND'''
+*An unpopulated 20-pin DIP position sits between M3 and M11
+===Reverse-Engineering Notes===
+#The MC6809 + MC6821 + dual MC6840 set is a textbook Motorola control core. The two PTMs are well-suited to ''measuring'' the voltage-PWM and current-PWM the 127 board returns over J-3 (gate / capture), and to generating the volt-hour and timed-run intervals for the four operating modes.
+#J-3 is wired pin-for-pin to the 127 board's J-16, so the 125B PIA directly drives that interface: HV-enable, DAC clock / data / strobe out; circuit open / shorted / unknown status in. The keypad scan / display strobes go to the front panel on J-2.
+#The Signetics CK2605 FPGA (M7) handles glue logic — address decoding and control sequencing — alongside the discrete 74HC138 / HC00 / HC132 gates.
+#The S-8054 voltage detector (M10) provides power-on reset and brown-out supervision, gating the CPU and protecting the battery-backed SRAM during power transitions.
+#The ICL7660 makes a local −5 V rail for the analog / op-amp section rather than relying on the 127 board's ±15 V.
-==OEM No. 127A — HV Controller Board==
+===Items Still to Confirm===
-This is the analog/digital control board that bridges the front-panel microprocessor and the high-voltage power module. It accepts a digital setpoint from the μC, generates two PWM drive signals to control the HV switcher, and reports back the actual HV and HC values via a frequency-isolated telemetry path. It also handles fault detection and shutdown latching.
+*Identify the J-4 / J-5 harnesses
+*Dump the CK2605 (M7) configuration / determine its logic role
+*Determine J2 pinout to front panel board
+==OEM No. 127 (A/B) — HV Controller Board==
+This is the analog/digital control board that bridges the front-panel microprocessor and the high-voltage power module. It accepts a digital setpoint from the μC, generates two PWM drive signals to control the HV switcher, and reports back the actual HV and HC values via a frequency-isolated telemetry path. It also handles fault detection and shutdown latching.<gallery mode="slideshow">
+File:BIO-RAD OEM NO 127A Top.jpg|'''127A''' - Top of board, J-16 and optocouplers in bottom left
+File:BIO-RAD OEM NO 127A Bottom.jpg|'''127A''' - Bottom of board, cutout under optocouplers in top left for high voltage isolation
+File:BIO-RAD OEM NO 127B Top.jpg|'''127B''' - Top of board, J-16 and optocouplers in top right
+File:BIO-RAD OEM NO 127B Bottom.jpg|'''127B''' - Bottom of board, cutout under optocouplers in top left for high voltage isolation
+</gallery>
 ===Connector Map===
@@ Line 115: / Line 214: @@
 |}
-=== J-12 Power-Input Topology ===
+===J-12 Power-Input Topology===
+[[File:BIO-RAD OEM NO 127B Conn J12.jpg|thumb|alt=|none]]
 J-12 carries three transformer secondary windings plus a single ground-tie wire. The transformer itself has no center tap or earthed reference — the system ground is '''established on the board''' by bonding the negative DC output of one rectifier to the positive DC output of another, using the lone green wire. This stacks two of the rectified supplies end-to-end to produce the bipolar ±V<sub>unreg</sub> rails feeding the ±15 V analog regulators, while the third (blue) winding feeds an independent positive rail for the digital regulators.
-==== Stacked Topology ====
+====Stacked Topology====
 <pre>
@@ Line 148: / Line 249: @@
 </pre>
-==== Wire Color Map ====
+====Wire Color Map====
 {| class="wikitable"
-! Wire !! Conductors !! Function !! Feeds
+!Wire!!Conductors!!Function!!Feeds
 |-
-| '''Yellow''' || pair || Secondary winding #1, feeds bridge rectifier whose "+" output becomes +V<sub>unreg</sub> || +15 V regulator (REG2)
+|'''Yellow'''||pair||Secondary winding #1, feeds bridge rectifier whose "+" output becomes +V<sub>unreg</sub>||+15 V regulator (REG2)
 |-
-| '''Red''' || pair || Secondary winding #2, feeds bridge rectifier whose "−" output becomes −V<sub>unreg</sub> || −15 V regulator (REG1)
+|'''Red'''||pair||Secondary winding #2, feeds bridge rectifier whose "−" output becomes −V<sub>unreg</sub>||−15 V regulator (REG1)
 |-
-| '''Green''' || single || Ground bond — ties "−" of the yellow rectifier to "+" of the red rectifier, establishing the 0 V system reference || Analog ground for the entire board
+|'''Green'''||single||Ground bond — ties "−" of the yellow rectifier to "+" of the red rectifier, establishing the 0 V system reference||Analog ground for the entire board
 |-
-| '''Blue''' || pair || Secondary winding #3 (independent), feeds bridge rectifier for the positive logic rail || +12 V (REG3) and +5 V (REG4) regulators
+|'''Blue'''||pair||Secondary winding #3 (independent), feeds bridge rectifier for the positive logic rail||+12 V (REG3) and +5 V (REG4) regulators
 |}
-==== Notes on the Topology ====
+====Notes on the Topology====
+*The transformer has '''three independent floating secondaries''' — no center tap is brought out. The bipolar ±15 V rail pair is synthesized on the board by stacking two single-ended supplies via the green ground-tie wire.
+*The green wire is a '''current-carrying ground return''', not just a reference. The imbalance current between the +15 V and −15 V loads flows through it back to the rectifier diodes, so it should be a reasonable gauge and routed for low loop inductance. Lifting it during service work will collapse the entire analog ground reference of the board.
+*Because the "+" pin of the red bridge rectifier is bonded to ground, the red supply's '''negative''' DC output is the rail that goes down to the −15 V regulator. This is normal for a stacked topology but can be confusing if you expect the rectifier "+" pin to be the rail output.
+*Keeping the digital +5 V / +12 V supply on its own winding (blue) isolates digital switching noise from the ±15 V analog rails, which carry the precision references for the AD7543 DAC and the AD654 V/F converters.
-* The transformer has '''three independent floating secondaries''' — no center tap is brought out. The bipolar ±15 V rail pair is synthesized on the board by stacking two single-ended supplies via the green ground-tie wire.
+===J-16 Data, Status and Telemetry===
-* The green wire is a '''current-carrying ground return''', not just a reference. The imbalance current between the +15 V and −15 V loads flows through it back to the rectifier diodes, so it should be a reasonable gauge and routed for low loop inductance. Lifting it during service work will collapse the entire analog ground reference of the board.
+[[File:BIO-RAD OEM NO 127B Conn J16.jpg|none|thumb]]
-* Because the "+" pin of the red bridge rectifier is bonded to ground, the red supply's '''negative''' DC output is the rail that goes down to the −15 V regulator. This is normal for a stacked topology but can be confusing if you expect the rectifier "+" pin to be the rail output.
+J-16 carries four data lines to an on-board [https://wiki.recessim.com/w/images/f/fc/AD7543.PDF AD7543] Digital to Analog Converter (DAC) which selects the voltage generated by the power supply. 0 - 4095 is the valid range to set ~20V to 3000V in 0.7V increments. It also has PWM outputs for voltage and current to monitor actual values and three additional I/O lines to signal Circuit Open, Circuit Shorted and one Circuit Unknown, possibly to signal a ground fault condition per the user manual. This connector goes straight to optocouplers so the control side is isolated from the high voltage side.
-* Keeping the digital +5 V / +12 V supply on its own winding (blue) isolates digital switching noise from the ±15 V analog rails, which carry the precision references for the AD7543 DAC and the AD654 V/F converters.
+====Pin Definitions====
+{| class="wikitable"
+|+J-16 Pinout
+!Position
+!Function
+!Direction
+!To IC pin
+!Notes
+|-
+|1
+| +5V
+|Input
+|PC1-1,3,5,7
+|Supplied by the logic board to the Optocoupler drivers used to send data to the DAC
+|-
+|2
+|Voltage PWM
+|Output
+|PC2-16
+|PWM output corresponding to voltage level
+|-
+|3
+|Current PWM
+|Output
+|PC2-14
+|PWM output corresponding to current draw
+|-
+|4
+|Circuit Unknown
+|Output
+|PC3-4
+|Possibly a ground fault indicator
+|-
+|5
+|Circuit Open
+|Output
+|PC2-12
+|Indicates if a load is connected to the High Voltage output
+|-
+|6
+|Circuit Shorted
+|Output
+|PC2-10
+|Indicates if the High Voltage output is shorted
+|-
+|7
+|HV Enable
+|Input
+|PC1-8
+|Active Low - Set low to enable HV output control by DAC, set high to disable HV supply
+|-
+|8
+|DAC Clock
+|Input
+|PC1-6
+|Active Low - 12 clock cycles
+|-
+|9
+|DAC Data
+|Input
+|PC1-4
+|Active Low - Data MSB
+|-
+|10
+|DAC Strobe
+|Input
+|PC1-2
+|Active High - Strobe signal at the end of the data load
+|-
+|11, 12
+|GND
+|Input
+|PC3-3
+PC2-9,11,13,15
+|Ground supplied by logic board to Optocoupler receivers used to communicate back to logic board
+|}
+====Timing Information====
+<gallery widths="300" mode="slideshow">
+File:BIO-RAD 3000Xi DAC Data Capture.png
+File:BIO-RAD 3000Xi DAC Data Capture - Enable to Clock.png|HV Enable low to start of data
+File:BIO-RAD 3000Xi DAC Data Capture - Clock Timing.png|Clock signal timing
+File:BIO-RAD 3000Xi DAC Data Capture - Data Timing.png|Data signal timing, centered within clock
+File:BIO-RAD 3000Xi DAC Data Capture - Clock to Strobe.png|End of clock to strobe timing
+</gallery><br />
 ===Active Components===
@@ Line 184: / Line 374: @@
 !Part Number!!Marking!!Package!!Function!!Datasheet
 |-
-|'''Analog Devices AD7543JN'''||"AD7543JN"||16-DIP||CMOS 12-bit '''serial-input''' monolithic multiplying DAC, R-2R ladder. Has an internal 12-bit serial-in parallel-out shift register (Register A) plus a separate 12-bit DAC input register (Register B), so the chip accepts serial setpoint data directly from the μC — no external shift register required. The two-register architecture lets the μC clock in a new code while the DAC continues to hold the previous value, then transfer it cleanly with a LOAD pulse. Asynchronous CLEAR input zeroes Register B for safe initialization. With 12-bit resolution this gives '''~0.7 V resolution at 3000 V full-scale''' — consistent with Bio-Rad's published 1 V step granularity. The "multiplying" feature is convenient because V<sub>REF</sub> can be scaled by an external precision reference for absolute-voltage trim.||[https://www.analog.com/en/products/ad7543.html AD7543 product page] · [https://www.alldatasheet.com/datasheet-pdf/pdf/48235/AD/AD7543.html PDF]
+|'''Analog Devices AD7543JN'''||"AD7543JN"||16-DIP||CMOS 12-bit '''serial-input''' monolithic multiplying DAC, R-2R ladder. Has an internal 12-bit serial-in parallel-out shift register (Register A) plus a separate 12-bit DAC input register (Register B), so the chip accepts serial setpoint data directly from the μC — no external shift register required. The two-register architecture lets the μC clock in a new code while the DAC continues to hold the previous value, then transfer it cleanly with a LOAD pulse. Asynchronous CLEAR input zeroes Register B for safe initialization. With 12-bit resolution this gives '''~0.7 V resolution at 3000 V full-scale''' — consistent with Bio-Rad's published 1 V step granularity. The "multiplying" feature is convenient because V<sub>REF</sub> can be scaled by an external precision reference for absolute-voltage trim.||[https://www.analog.com/en/products/ad7543.html AD7543 product page] · [https://wiki.recessim.com/w/images/f/fc/AD7543.PDF PDF]
 |}
@@ Line 224: / Line 414: @@
 !Part Number!!Marking!!Package!!Function!!Datasheet
 |-
-|'''TLP621-4''' (×2)||"T8K TLP621-4 GB"||16-DIP||Quad transistor-output optocoupler, 5 kVrms isolation, CTR 100–600 %. Together they provide 8 isolated digital channels — sufficient for the AD7543's serial interface (SRI data, STB clock, LD load, CLR clear), master enable, fault status, plus the two AD654 frequency-out telemetry channels.||[https://uk.farnell.com/toshiba/tlp621-4-gb/optocoupler-quad-5kv-transtr-o/dp/1225839 Farnell page]
+|'''TLP621-4''' (×2)||"T8K TLP621-4 GB"||16-DIP||Quad transistor-output optocoupler, 5 kVrms isolation, CTR 100–600 %. Together they provide 8 isolated digital channels — sufficient for the AD7543's serial interface (SRI data, STB clock, LD load, CLR clear), master enable, fault status, plus the two AD654 frequency-out telemetry channels.||[[:File:TLP621 datasheet.pdf|Datasheet]]
 |-
-|'''TLP621''' (×1)||"T7K P621"||4-DIP||Single-channel version. Probably an additional status / interlock line, or a high-priority signal kept on its own isolation domain.||[https://toshiba.semicon-storage.com/us/semiconductor/product/isolators-solid-state-relays.html Toshiba family]
+|'''TLP621''' (×1)||"T7K P621"||4-DIP||Single-channel version. Probably an additional status / interlock line, or a high-priority signal kept on its own isolation domain.||[[:File:TLP621 datasheet.pdf|Datasheet]]
 |}
@@ Line 232: / Line 422: @@
 {| class="wikitable"
-!Position!!Part Number!!Marking!!Output!!Datasheet
+!Position!!Part Number!!Output!!Datasheet
 |-
-|'''REG1'''||Fairchild '''μA79M15A''' (Korea)||"μA79M15A UC871x KOREA"||'''−15 V''' analog rail||[https://www.ti.com/lit/ds/symlink/lm7900.pdf 79xx PDF (TI)]
+|'''REG1'''||7805||'''+5V''' Digital Rail||[https://www.ti.com/lit/ds/symlink/lm340.pdf LM340 PDF (TI)]
 |-
-|'''REG2'''||Fairchild '''μA 78M15''' (Korea)||"μA 78M15 UC8704 KOREA"||'''+15 V''' analog rail||[https://www.ti.com/lit/ds/symlink/lm340.pdf 78xx PDF (TI)]
+|'''REG2'''||7815||'''+15 V''' analog rail||[https://www.ti.com/lit/ds/symlink/lm340.pdf 78xx PDF (TI)]
 |-
-|'''REG3''' ''(or REG4)''||National '''LM340T-12'''||"EM340T12 7812 P+" 8730||'''+12 V''' rail||[https://www.ti.com/lit/ds/symlink/lm340.pdf LM340 PDF (TI)]
+|'''REG3'''||7915||'''−15 V''' analog rail
+|[https://www.ti.com/lit/ds/symlink/lm79.pdf 79xx PDF (TI)]
 |-
-|'''REG4''' ''(or REG3)''||Fairchild '''μA 78M05''' (Korea)||"μA 78M05 UC8731 KOREA"||'''+5 V''' digital rail||[https://www.ti.com/lit/ds/symlink/lm340.pdf 78M PDF (TI)]
+|'''REG4'''||7812||'''+12 V''' rail||[https://www.ti.com/lit/ds/symlink/lm340.pdf 78M PDF (TI)]
 |}
-<div style="border-left:4px solid #f0ad4e; background:#fcf8e3; padding:0.5em 1em; margin:1em 0;">
-'''Note:''' REG3 vs REG4 silkscreen position needs confirmation against the TO-220 part numbers — only the REG1/REG2 silkscreen was clearly visible in image 3.
-</div>
 ===Passive Components===
@@ Line 290: / Line 477: @@
 ----
-==OEM No. 125B==
-''Module not yet examined. Photos and reverse-engineering pending.''
 ==OEM No. 126C==
@@ Line 319: / Line 502: @@
 Multi-secondary line-frequency transformer visible at the top-left of the chassis. Has at least three independent floating secondary windings brought out to the OEM No. 127A controller board via J-12:
-* '''Yellow pair''' — secondary winding #1, feeds the +15 V analog rail
+*'''Yellow pair''' — secondary winding #1, feeds the +15 V analog rail
-* '''Red pair''' — secondary winding #2, feeds the −15 V analog rail
+*'''Red pair''' — secondary winding #2, feeds the −15 V analog rail
-* '''Blue pair''' — secondary winding #3, feeds the +12 V and +5 V digital rails
+*'''Blue pair''' — secondary winding #3, feeds the +12 V and +5 V digital rails
 A single '''green wire''' also exits the harness at J-12 to bond the rectifier outputs into a stacked bipolar topology (see [[#J-12 Power-Input Topology|J-12 Power-Input Topology]]).