ATSAM4C32: Difference between revisions
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===Locking Mechanism=== | ===Locking Mechanism=== | ||
The SAM4C32 makes use of general-purpose non-volatile memory (GPNVM) bits to control locking, boot mode and memory plane selection as seen below.[[File:ATSAM4C32 Table 8-3.png|alt=]] | The SAM4C32 makes use of general-purpose non-volatile memory (GPNVM) bits to control locking, boot mode and memory plane selection as seen below.[[File:ATSAM4C32 Table 8-3.png|alt=]] | ||
'''''Below is extracted from Microchip datasheet DS60001717B.'''''<blockquote> | |||
====Security Bit==== | ====Security Bit==== | ||
The SAM4C features a security bit based on a specific General-purpose NVM bit (GPNVM bit 0). When the security is enabled, any access to the Flash, SRAM, core registers and internal peripherals, either through the SW-DP/JTAG-DP interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash. | The SAM4C features a security bit based on a specific General-purpose NVM bit (GPNVM bit 0). When the security is enabled, any access to the Flash, SRAM, core registers and internal peripherals, either through the SW-DP/JTAG-DP interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash. | ||
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The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). | The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). | ||
The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0. | The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0.</blockquote><br /> | ||
===Reset vs Power Cycle=== | ===Reset vs Power Cycle=== | ||
TBD | TBD | ||