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This is a complex device with a 16 bit CPU, Xilinx 95xx CPLD, Custom Alesis chip (Gate array, PAL, GAL, OTP CPLD?) SRAM, NOR flash 512kb, logic and switching for bus arbitration. BREQ Bus request is a very involved circuit. Also CE# Chip Enable NOR Flash is connected through a complicated muxing circuit. The Alesis custom IC handles the WE# Write Enable to the NOR Flash.

The Device is quite old school, this . This was built for the early generation of ADAT/TDIF machines, still using physical tape. Though tape is not necessary for operation, the sync requirements of locking digital audio, using analogue tape, add a lot of adds complexity.