Roland DIF-AT: Difference between revisions

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==Device Overview==

This is a complex device with a 16 bit CPU, Xilinx 95xx CPLD, Custom Alesis chip (Gate array, PAL, GAL, OTP CPLD?) SRAM, NOR flash 512kb, logic and switching for bus arbitration. BREQ Bus request is a very involved circuit. Also CE# Chip Enable NOR Flash is connected through a complicated muxing circuit.

This is a complex device with a 16 bit CPU, Xilinx 95xx CPLD, Custom Alesis chip (Gate array, PAL, GAL, OTP CPLD?) SRAM, NOR flash 512kb, logic and switching for bus arbitration. BREQ Bus request is a very involved circuit. Also CE# Chip Enable NOR Flash is connected through a complicated muxing circuit. The Alesis custom IC handles the WE# Write Enable to the NOR Flash.

The Device is quite old school~~, this~~ was built for the early generation of ADAT/TDIF machines, still using physical tape. Though tape is not necessary for operation, the sync requirements of locking digital audio, using analogue tape, ~~add a lot of~~ complexity.

The Device is quite old school. This was built for the early generation of ADAT/TDIF machines, still using physical tape. Though tape is not necessary for operation, the sync requirements of locking digital audio, using analogue tape, adds complexity.

It has 2 buttons on the PCB: 1 - RESET, reset circuit and IC 2 - Launch monitor diagnostic mode. A 50 pin header provides easy access to most address lines and relevant (to operation) CPU/RAM/Flash lines. This will be convenient to run a logic capture during boot and operation later.

@@ Line 40: / Line 40: @@
 ==Device Overview==
-This is a complex device with a 16 bit CPU, Xilinx 95xx CPLD, Custom Alesis chip (Gate array, PAL, GAL, OTP CPLD?) SRAM, NOR flash 512kb, logic and switching for bus arbitration.  BREQ Bus request is a very involved circuit.  Also CE# Chip Enable NOR Flash is connected through a complicated muxing circuit.
+This is a complex device with a 16 bit CPU, Xilinx 95xx CPLD, Custom Alesis chip (Gate array, PAL, GAL, OTP CPLD?) SRAM, NOR flash 512kb, logic and switching for bus arbitration.  BREQ Bus request is a very involved circuit.  Also CE# Chip Enable NOR Flash is connected through a complicated muxing circuit.  The Alesis custom IC handles the WE# Write Enable to the NOR Flash.
-The Device is quite old school, this was built for the early generation of ADAT/TDIF machines, still using physical tape.  Though tape is not necessary for operation, the sync requirements of locking digital audio, using analogue tape, add a lot of complexity.
+The Device is quite old school.  This was built for the early generation of ADAT/TDIF machines, still using physical tape.  Though tape is not necessary for operation, the sync requirements of locking digital audio, using analogue tape, adds complexity.
 It has 2 buttons on the PCB: 1 - RESET, reset circuit and IC  2 - Launch monitor diagnostic mode.  A 50 pin header provides easy access to most address lines and relevant (to operation) CPU/RAM/Flash lines.  This will be convenient to run a logic capture during boot and operation later.