83
edits
Changes
m
The Device is quite old school. This was built for No info could be found on the early generation of ADAT/TDIF machinesAlesis chip, still using physical tape. Though tape is not necessary searching for operation, the sync requirements of locking digital audio, using analogue tape, adds complexitynumerous IC markings revealed nothing.
It has 2 buttons on The Device is quite old school. This was built for the PCB: 1 - RESETearly generation of ADAT/TDIF machines, reset circuit and IC 2 - Launch monitor diagnostic modestill using physical tape. A 50 pin header provides easy access to most address lines and relevant (to Thankfully a tape machine is not necessary for operation) CPU/RAM/Flash lines. This will be convenient The sync requirements of locking digital audio using analogue tape definitely adds complexity to run a logic capture during boot and operation laterthis system.
I beeped out Device has 2 buttons on the 50 pin connector PCB: 1 - Many pins have multiple connections. RESET, reset circuit and IC Happily; the vias were not tented 2 - this was a long endeavour even with Launch monitor diagnostic mode.
→Device Overview: JTAG programming
==Device Overview==
This is a complex device with a 16 bit CPU, Xilinx 95xx CPLD, Custom Alesis chip (Gate array, PAL, GAL, OTP CPLD?) SRAM, NOR flash 512kb, logic and switching for bus arbitration. BREQ Bus request is a very involved circuit. Also CE# Chip Enable NOR Flash is connected through a complicated muxing circuit. The Alesis custom IC handles the WE# Write Enable to the NOR Flash.
A 50 pin header provides easy access to most address lines and relevant (to operation) CPU/RAM/Flash lines. This will be convenient to run a logic capture during boot and operation later. I beeped out the 50 pin connector - Many pins have multiple connections. Happily; the vias were not tented - this was a long endeavour even with continuity through the vias : ) Below, the findings and some general notes: <gallery>
File:DIFat 50 pin header1 .png|alt=dif at pin header pins 1 - 16|header pins 1 - 16
File:DIFat 50 pin header2.png|alt=header pins 16 - 24|header pins 16 - 24
</gallery>
== JTAG/Programming/Firmware ==
The device has two levels of firmware: NOR Flash and CPLD bitstream. The Xilinx is an older model XC95144 which is programmed over JTAG. However, due to the architecture, bitstream cannot be read out over JTAG (even if unlocked). It still seems strange to me that, this is a 100 pin CPLD, and only 4 inputs and 4 outputs are used! (RBUS data solely, 8 channels L/R).
Perhaps Roland just had a load of these in house already and it was cheaper to use them than get a smaller device. Or maybe it was the only suitable device in that range?
JTAG pads are exposed on the PCB as seen in the image above. I could connect to these to read the CPLD. Pretty soon they were pulled off the board, and I had to solder a pin to the leg temporarily to continue reading data. I connected using Bluetag, OpenOCD and XC3SPROG (open source Xilinx CLI) and was eventually able to read back ID codes and find IR Len etc. I was happy it was still alive!
At some point I will get a Xilinx Platform Cable to attempt to read the bitstream for archival purposes. However at this stage I'd had to get a few probes etc and didn't really want to get a Xilinx only device. I've had great luck with unlocked devices so far though, everything I've looked at has been open or level 1 : )
==Extract Firmware==
I used a TL48 programmer with a 48pin TTSOP to read the NOR Flash firmware contents -
Below in the image are the settings needed for a good read. The NOR flash is 16 bit wide, but the CPU is reading it in 8 bit mode (8 bit mode pin is tied low). SHARP LH28F400BVE Parallel NOR Flash 512kb. The chip is from the late 1990s as the device is also, turn of the century 2000s.