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After some months working on this, and seeing the LEDs blink again (it took an embarrassingly long time to realise they were pulled high) I was satisfied I could take a short break from it. I will complete the repair by fully testing it and running the UART Monitor program.
Adeeper look at the Alesis chip: It is possible that it is a pre-programmed CPLD, but that it has JTAG access. More likely it's an ASIC rather than OTP CPLD or GAL, PAL. Still though, it would be interesting to reveal something about it. As I said it's not on the JTAG chain here anyway.
I will update this when the device is fully tested. For now, be assured that it's back together, repaired, and starting to boot. There could be some small issues, which can be discovered and fixed with the UART function. I could only continue the marathon with a reboot myself.
Here are some general pinout notes on the DIF-AT RBUS and Digital Audio flow, and the connections to the Alesis Chip (which seems to do all the heavy lifting as regards audio and timing) All audio formats go directly into the Alesis chip, and it handles so much, audio formats, inputs, - BREQ bus arbitration, WE to Flash, CE with mux to Flash, that it must be an ASIC. The Xilinx chip is handling RBUS signals only, after they leave the Alesis chip, they go into the Xilinx CPLD, and leave the DIF AT via an inverter. I will inspect the signals before and after the Xilinx chip to see how it is processing the data after the Alesis chip.
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