Changes

|[[#Mains Transformer|Mains transformer]]||Multi-tap secondary line transformer||Not yet Partially documented

│ ┌────────────┐ ┌────────────┐ ┌─────────────────┐ │ │ │ Opto-iso. │─▶│ Logic + │─▶| TC4584 │─▶│ AD7541 AD7543 12-bit │ │ │ │ rcv (TLP) │ │ shift reg Schmitt │ │ multiplying serial-in DAC │ │ │ └────────────┘ └────────────┘ └────────┬────────┘ │

|'''J-12'''||In||Multi-tap Three transformer secondaries → plus a ground-tie wire — feeds the on-board rectifierrectifiers and ±15 V / +12 V /regulator section+5 V regulators (see [[#J-12 Power-Input Topology|J-12 Power-Input Topology]] below)

|'''J-16'''||In/Out||Ribbon to embedded controller — serial DAC code in, telemetry and status out via optocouplers

* Keeping the digital +5 V / +12 V supply on its own winding (blue) isolates digital switching noise from the ±15 V analog rails, which carry the precision references for the AD7541 AD7543 DAC and the AD654 V/F converters.

|'''Analog Devices AD7541JNAD7543JN'''||"AD7541JNAD7543JN"||1816-DIP||CMOS 12-bit monolithic '''multiplying DACserial-input'''monolithic multiplying DAC, R-2R ladder. Receives Has an internal 12-bit serial-in parallel-out shift register (Register A) plus a separate 12-bit DAC input register (Register B), so the digital chip accepts serial setpoint data directly from the μC and converts it — no external shift register required. The two-register architecture lets the μC clock in a new code while the DAC continues to an analog reference into hold the IR3M02 control loopprevious value, then transfer it cleanly with a LOAD pulse. Asynchronous CLEAR input zeroes Register B for safe initialization. With 12-bit resolution this gives '''~0.7 V resolution at 3000 V full-scale''' — consistent with Bio-Rad's published 1 V step granularity. The "multiplying" feature is convenient because V_REF can be scaled by an external precision reference for absolute-voltage trim.||[https://www.analog.com/media/en/technical-documentation/data-sheetsproducts/ad7541aad7543.pdf AD7541A PDF (current)html AD7543 product page] · [https://www.alldatasheet.com/datasheet-pdf/pdf/6627948235/INTERSILAD/AD7541AD7543.html Intersil AD7541 PDF]

|'''TC4011BP'''||"TOSHIBA 8838B TC4011BP JAPAN"||14-DIP||Quad 2-input NAND gate. Likely used to combine fault / interlock / reset signals into the IR3M02 shutdown line and possibly to gate the AD7543 control inputs.||[https://toshiba.semicon-storage.com/eu/semiconductor/product/general-purpose-logic-ics/detail.TC4011BP.html Toshiba page] · [https://www.alldatasheet.com/datasheet-pdf/pdf/31627/TOSHIBA/TC4011BP.html PDF]

|'''TC4013BP'''||"TOSHIBA 8836HB TC4013BP JAPAN"||14-DIP||Dual D-type flip-flop with set/reset. Used together with TC4011/TC4025 to implement serial-to-parallel conversion Strong candidate for the AD7541 inputs ''and'fault latch''' — set by a comparator output from J-15 (short / overcurrent / arc), output ties into the IR3M02 shutdown pin and stays latched until the μC issues an explicit reset. The second flip-flop may serve as a sync stage or as a faultdivide-by-2 in an AD654 gate-latch for the protection circuittiming chain.||[https://toshiba.semicon-storage.com/info/TC4013BF_datasheet_en.pdf Toshiba PDF]

|'''TC4025BP'''||"TOSHIBA 8844HB TC4025BP JAPAN"||14-DIP||Triple 3-input NOR gate. Typical use in this kind of design: combining multiple shutdown sources (over-current, over-voltage, interlock-open, μC-stop) into a single active-high enable signal.||[https://toshiba.semicon-storage.com/info/TC4025BF_datasheet_en.pdf Toshiba PDF]

|'''TC4584BP'''||"TOSHIBA 8848H TC4584BP JAPAN"||14-DIP||Hex Schmitt-trigger inverter — cleans . '''Confirmed''' to sit in the signal path between the input optocoupler bank and the AD7543, cleaning up the slow optocoupler-output edges from the optocoupler outputs and inverting them before they enter reach the DAC's clocked inputs (SRI / STB / LD / CLR), which require sharp transitions. With 6 cells available and 4 used for the synchronous logicDAC interface, up to 2 cells remain — likely used either for additional input cleanup (master enable, fault input from J-15) or configured as an RC oscillator providing a local time-base for AD654 gate timing.||[https://www.datasheetcatalog.com/datasheets_pdf/T/C/4/5/TC4584BP.shtml PDF]

|'''TLP621-4''' (×2)||"T8K TLP621-4 GB"||16-DIP||Quad transistor-output optocoupler, 5 kVrms isolation, CTR 100–600 %. Together they provide 8 isolated digital channels — sufficient for the AD7543's serial DAC-load interface (SRI data + , STB clock + strobe, LD load, CLR clear), reset / master enable, fault status, plus the two AD654 frequency-out telemetry channels.||[https://uk.farnell.com/toshiba/tlp621-4-gb/optocoupler-quad-5kv-transtr-o/dp/1225839 Farnell page]

|'''TLP621''' (×1)||"T7K P621"||4-DIP||Single-channel version. Probably an additional status / interlock line, or a high-priority signal kept on its own isolation domain.||[https://toshiba.semicon-storage.com/us/semiconductor/product/isolators-solid-state-relays.html Toshiba family]

#The '''AD7541 AD7543 12-bit serial-input DAC''' confirms this is a fully digital setpoint architecture, not a potentiometer-driven supply. The controller writes clocks a 12-bit code; into the AD7541 produces DAC's internal Register A through one optocoupler channel (SRI) timed by another (STB), then issues a LOAD pulse on a precise reference that third channel to transfer the new code to the IR3M02 servo loops trackDAC output (Register B). With 4096 codes across 3000 V full-scale, that's ~0.73 V LSB — Bio-Rad spec'd 1 V steps, which matches.#Because the two TLP621AD7543 has its own internal serial-4 quads only provide 8 isolated channels and the AD7541 has 12 parallel data inputsin shift register, the data must be '''shifted in serially''' on the board. The TC4013 / TC4011 / TC4025 logic cluster between the optocouplers and the DAC is doing exactly that — not performing serial-to-parallel conversion plus for the DAC'''. Instead, that logic most likely handles: (a) fault-latching (TC4013 D-flip-flop set by a comparator output from J-15, output ties into the IR3M02 shutdown pin until the μC issues a strobe latchreset), (b) generating local timing or gate windows for the AD654 measurement cycle, and/or (c) combining manual-reset, interlock, and over-temperature signals into the master enable line.#The '''AD654 + TLP621-4 telemetry path''' is the classical isolated-precision-measurement trick. Two channels — one for HV, one for HC — give the μC the data it needs to display "actual" values and run constant-power calculations. Frequency-domain transmission across the optocoupler sidesteps CTR drift and aging.#The '''TC4013 dual flipTC4584 Schmitt is confirmed in the optocoupler-to-flopDAC path.''' likely also serves as Each of the faultfour AD7543 control signals (SRI, STB, LD, CLR) passes through one Schmitt-latch: a comparator inverter cell after the optocoupler before reaching the DAC. Note that the TC4584 cells are '''inverting''' — the logic polarity at the DAC pin is opposite the polarity at the optocoupler output from J-15 , which matters when probing. Combined with the optocoupler's own inversion (short / overcurrent) sets a latch that the output transistor pulls low when the IR3M02 shutdown pin until LED is on), the net polarity from μC issues a resetto DAC is non-inverting.#The '''TC4584 SchmittJ-12 power-input topology''' at (three independent floating secondaries with on-board ground synthesis via the green ground-tie wire) means the digital input entire OEM 127A board is correct practice for cleaning referenced to ''its own'' analog ground, not chassis. Anything probing this board during operation must reference scope grounds to that node, not to chassis or earth, to avoid blowing up the output side of the optocoupler before any synchronous logicsecondary windings or injecting ground loops.

*Trace the 8 9 optocoupler channels at J-16 (8 across the two TLP621-4 quads plus the 1 in the TLP621 single) and assign each a function . Expected set: AD7543 SRI / STB / LD / CLR (4), master ENABLE (1), FAULT status out (1), HV frequency out (1), HC frequency out (DATA 1), plus 1 reserved/ CLK interlock.*Determine what role the TC4013 / LATCH TC4011 / RESET / VTC4025 logic plays now that the DAC handles its own serial-to-FREQ parallel conversion (fault latch and/ Ior AD654 gate-FREQ / +2 sparetiming oscillator are the leading hypotheses).

''Switch-mode housekeeping supply visible at the right side of the chassis. Not yet examined in detail. Provides the bulk DC rails fed into J-12 of the OEM No. 127A controller board.''

''Multi-tap secondary line-frequency transformer visible at the top-left of the chassis. Secondaries route Has at least three independent floating secondary windings brought out to the rectifier and on-board regulators of the OEM No. 127A controller boardvia J-12: * '''Yellow pair''' — secondary winding #1, feeds the +15 V analog rail* '''Red pair''' — secondary winding #2, feeds the −15 V analog rail* '''Blue pair''' — secondary winding #3, feeds the +12 V and +5 V digital rails A single '''green wire''' also exits the harness at J-12 to bond the rectifier outputs into a stacked bipolar topology (see [[#J-12 Power-Input Topology|J-12 Power-Input Topology]]).  Voltage taps and current ratings TBD.''Additional secondaries (if any) feeding the [[#High Voltage Generation Module|HV generation module]] are routed separately and have not yet been documented.