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=== J-12 Power-Input Topology ===
J-12 carries three transformer secondary windings plus a single ground-tie wire. The transformer itself has no center tap or earthed reference — the system ground is '''established on the board''' by bonding the negative DC output of one rectifier to the positive DC output of another, using the lone green wire. This stacks two of the rectified supplies end-to-end to produce the bipolar ±V<sub>unreg</sub> rails feeding the ±15 V analog regulators, while the third (blue) winding feeds an independent positive rail for the digital regulators.
==== Stacked Topology ====
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==== Wire Color Map ====
{| class="wikitable"
! Wire !! Conductors !! Function !! Feeds
|-
| '''Yellow''' || pair || Secondary winding #1, feeds bridge rectifier whose "+" output becomes +V<sub>unreg</sub> || +15 V regulator (REG2)
|-
| '''Red''' || pair || Secondary winding #2, feeds bridge rectifier whose "−" output becomes −V<sub>unreg</sub> || −15 V regulator (REG1)
|-
| '''Green''' || single || Ground bond — ties "−" of the yellow rectifier to "+" of the red rectifier, establishing the 0 V system reference || Analog ground for the entire board
|-
| '''Blue''' || pair || Secondary winding #3 (independent), feeds bridge rectifier for the positive logic rail || +12 V (REG3) and +5 V (REG4) regulators
|}
==== Notes on the Topology ====
* The transformer has '''three independent floating secondaries''' — no center tap is brought out. The bipolar ±15 V rail pair is synthesized on the board by stacking two single-ended supplies via the green ground-tie wire.* The green wire is a '''current-carrying ground return''', not just a reference. The imbalance current between the +15 V and −15 V loads flows through it back to the rectifier diodes, so it should be a reasonable gauge and routed for low loop inductance. Lifting it during service work will collapse the entire analog ground reference of the board.* Because the "+" pin of the red bridge rectifier is bonded to ground, the red supply's '''negative''' DC output is the rail that goes down to the −15 V regulator. This is normal for a stacked topology but can be confusing if you expect the rectifier "+" pin to be the rail output.* Keeping the digital +5 V / +12 V supply on its own winding (blue) isolates digital switching noise from the ±15 V analog rails, which carry the precision references for the AD7543 DAC and the AD654 V/F converters.
===Active Components===
!Part Number!!Marking!!Package!!Function!!Datasheet
|-
|'''Analog Devices AD7543JN'''||"AD7543JN"||16-DIP||CMOS 12-bit '''serial-input''' monolithic multiplying DAC, R-2R ladder. Has an internal 12-bit serial-in parallel-out shift register (Register A) plus a separate 12-bit DAC input register (Register B), so the chip accepts serial setpoint data directly from the μC — no external shift register required. The two-register architecture lets the μC clock in a new code while the DAC continues to hold the previous value, then transfer it cleanly with a LOAD pulse. Asynchronous CLEAR input zeroes Register B for safe initialization. With 12-bit resolution this gives '''~0.7 V resolution at 3000 V full-scale''' — consistent with Bio-Rad's published 1 V step granularity. The "multiplying" feature is convenient because V<sub>REF</sub> can be scaled by an external precision reference for absolute-voltage trim.||[https://www.analog.com/en/products/ad7543.html AD7543 product page] · [https[:File://www.alldatasheet.com/datasheet-pdf/pdf/48235/AD/AD7543.html PDF|PDF]]
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Multi-secondary line-frequency transformer visible at the top-left of the chassis. Has at least three independent floating secondary windings brought out to the OEM No. 127A controller board via J-12:
* '''Yellow pair''' — secondary winding #1, feeds the +15 V analog rail* '''Red pair''' — secondary winding #2, feeds the −15 V analog rail* '''Blue pair''' — secondary winding #3, feeds the +12 V and +5 V digital rails
A single '''green wire''' also exits the harness at J-12 to bond the rectifier outputs into a stacked bipolar topology (see [[#J-12 Power-Input Topology|J-12 Power-Input Topology]]).