LMS-6 Radiosonde: Difference between revisions
document the bit-synth interrupt |
Paul Rixon (talk | contribs) m Reformatted Card Edge Connector |
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| Line 140: | Line 140: | ||
{| class="wikitable" | {| class="wikitable" | ||
|+Card edge - 40-pin, looks like ISA spacing | |+Card edge - 40-pin, looks like ISA spacing | ||
!Pin Number | |||
!Function | |||
!Notes / Observations | |||
!Pin Number | !Pin Number | ||
!Function | !Function | ||
!Notes / Observations | !Notes / Observations | ||
|- | |- | ||
|1 | |1 | ||
|Vdd | |||
|U3 - Vdd | |||
U15 - Pin 4 | |||
|2 | |||
|Vdd | |||
|U3 - Vdd | |U3 - Vdd | ||
U15 - Pin 4 | U15 - Pin 4 | ||
|- | |- | ||
|3 | |3 | ||
| Line 163: | Line 162: | ||
U21 - Pin21 / PCLK | U21 - Pin21 / PCLK | ||
| | | | ||
|4 | |4 | ||
|U3 - Pin38/Vpp/ICCSEL | |U3 - Pin38/Vpp/ICCSEL | ||
| Line 173: | Line 171: | ||
|U3 - Pin39/RESET | |U3 - Pin39/RESET | ||
| | | | ||
|6 | |6 | ||
|U3 - Pin27 / PC4 / MISO / ICCDATA | |U3 - Pin27 / PC4 / MISO / ICCDATA | ||
| | |||
|- | |||
|7 | |||
|Vdd | |||
|U3 - Vdd | |||
U15 - Pin 4 | |||
|8 | |||
|Vdd | |||
|U3 - Vdd | |||
U15 - Pin 4 | |||
|- | |||
|9 | |||
|GND | |||
| | |||
|10 | |||
|GND | |||
| | | | ||
|- | |- | ||
| Line 181: | Line 194: | ||
|J5 - Pin 2 | |J5 - Pin 2 | ||
| | | | ||
|12 | |12 | ||
|U21 - Pin 20 - DCLK | |U21 - Pin 20 - DCLK | ||
| Line 189: | Line 201: | ||
|13 | |13 | ||
|SW1.4 | |SW1.4 | ||
U3 - Pin10/AIN3/PD3 | |U3 - Pin10/AIN3/PD3 | ||
51K resistor to ground | 51K resistor to ground | ||
|14 | |||
| | |||
| | |||
|- | |||
|15 | |||
|GND | |||
| | |||
|16 | |||
|GND | |||
| | | | ||
|- | |- | ||
|17 | |17 | ||
|SW1.2 | |SW1.2 | ||
U3 - Pin8/AIN1/PD1 | |U3 - Pin8/AIN1/PD1 | ||
51K resistor to ground | 51K resistor to ground | ||
|18 | |18 | ||
|SW1.1 | |SW1.1 | ||
U3 - Pin7/AIN0/PD0 | |U3 - Pin7/AIN0/PD0 | ||
51K resistor to ground | 51K resistor to ground | ||
|- | |||
|19 | |||
|GND | |||
| | |||
|20 | |||
|GND | |||
| | | | ||
|- | |- | ||
| Line 212: | Line 237: | ||
U3 - Pin19 | U3 - Pin19 | ||
|Appears to be some sort of test-mode select, checked before GPIO initialization. | |Appears to be some sort of test-mode select, checked before GPIO initialization. | ||
|22 | |||
| | |||
| | |||
|- | |- | ||
|23 | |23 | ||
| Line 217: | Line 245: | ||
U3 - Pin1/RDI | U3 - Pin1/RDI | ||
|Data bursts | |Data bursts | ||
|24 | |||
| | |||
| +5VDC ? | |||
|- | |- | ||
|25 | |||
| | |||
| | |||
|26 | |26 | ||
|GPS Data (38400 BPS) | |GPS Data (38400 BPS) | ||
Maybe not connected to U3? | Maybe not connected to U3? | ||
|Data bursts | |Data bursts | ||
|- | |||
|27 | |||
| | |||
| | |||
|28 | |||
| | |||
| | |||
|- | |||
|29 | |||
| | |||
| | |||
|30 | |||
| | |||
| +5VDC ? | |||
|- | |- | ||
|31 | |31 | ||
|BATT POS | |BATT POS | ||
| | |||
|32 | |||
| | |||
| | | | ||
|- | |- | ||
|33 | |||
|GND | |||
| | |||
|34 | |||
|GND | |||
| | |||
|- | |||
|35 | |||
| | |||
| | |||
|36 | |36 | ||
|SW1.3 | |SW1.3 | ||
U3 - Pin9/AIN2/PD2 | |U3 - Pin9/AIN2/PD2 | ||
51K resistor to ground | 51K resistor to ground | ||
|- | |||
|37 | |||
| | |||
| | | | ||
|38 | |38 | ||
|U3 - Pin18 / OCMP1_A / AIN10 / PF4 | |U3 - Pin18 / OCMP1_A / AIN10 / PF4 | ||
| Line 241: | Line 304: | ||
|RED WIRE | |RED WIRE | ||
| | | | ||
|40 | |40 | ||
|Battery voltage | |Battery voltage | ||
| Line 648: | Line 710: | ||
ST7 ADC AIN8 appears to be the only one used. | ST7 ADC AIN8 appears to be the only one used. | ||
=== Interrupts === | ===Interrupts=== | ||
* ei0_int | *ei0_int | ||
** Triggered by PortA.3 | **Triggered by PortA.3 | ||
** uses location 0xB2 as a shift register to output LSB first to CC1050's Data Input on PortF.4 | **uses location 0xB2 as a shift register to output LSB first to CC1050's Data Input on PortF.4 | ||
==Modifications== | ==Modifications== | ||