File:Xilinx CPLD.jpg

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Original file ‎(3,864 × 5,152 pixels, file size: 5.6 MB, MIME type: image/jpeg)

Summary

Xilinx CPLD and mux circuit. JTAG pads visible around pin 50 (silkscreen) and 81.

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Date/TimeThumbnailDimensionsUserComment
current16:56, 27 April 2026Thumbnail for version as of 16:56, 27 April 20263,864 × 5,152 (5.6 MB)RSS1 (talk | contribs)Xilinx CPLD and mux circuit. JTAG pads visible around pin 50 (silkscreen) and 81.

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