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To be filled in[[File:BIO-RAD_OEM_NO_125B_Top.jpg|thumb|right|300px|OEM No. 125B — top of board]]
→OEM No. 125B - CPU Control Board
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==OEM No. 125B - CPU Control Board==
The '''OEM No. 125B''' is the system CPU / control board — referenced in the [[#High-Level Block Diagram|block diagram]]. It runs the instrument firmware, drives the [[#OEM No. 126C|OEM No. 126C]] front-panel board (LCD, LED readouts, keypad) over J-2, and commands the [[#OEM No. 127 (A/B) — HV Controller Board|OEM No. 127]] HV controller over J-3 — sending the 12-bit DAC setpoint and reading back the voltage / current PWM telemetry and circuit-status lines. Run parameters are retained in battery-backed RAM. The board is built around the Motorola 6800-family set (MC6809 CPU, MC6821 PIA, dual MC6840 timers). Date codes place it at 1988; the EPROM is hand-labelled firmware "Xi 4.0". === Active Components === {| class="wikitable"! Ref !! Part !! Function|-| '''M1''' || Motorola MC6809P || 8-bit microprocessor — main CPU|-| '''M6''' || Motorola MC6821P || Peripheral Interface Adapter (PIA), two 8-bit parallel ports — front-panel keypad/display I/O and the J-3 handshake to the 127 board (HV-enable, DAC clock/data/strobe, circuit open/shorted/unknown status)|-| '''M4, M5''' || Motorola MC6840P (×2) || Programmable Timer Module, three 16-bit counter/timers each — volt-hour / run timing and capture of the voltage- and current-PWM telemetry from the 127 board|-| '''M2''' || Hitachi HN27256G-25 || 256 Kbit (32K×8) UV-EPROM — program store; windowed, V<sub>PP<br /sub>12.5 V, hand-labelled "Xi 4.0"|-| '''M3''' || Toshiba TC5564APL-15 || 64 Kbit (8K×8) static RAM — work / settings RAM, battery-backed by BAT1|-| '''M7''' || Signetics CK2605 || FPGA — system glue logic (address decode / control sequencing)|-| '''M11''' || Hitachi HD74LS640P || Octal inverting bus transceiver — data-bus buffer|-| '''M12''' || Motorola MC74HCT240 || Octal inverting 3-state buffer/line driver — address / control buffer|-| '''M8''' || Toshiba 74HC138AP || 3-to-8 line decoder — address decode / chip selects|-| '''M9''' || Toshiba TC74HC4020P || 14-stage binary ripple counter — clock division / timing|-| '''M14, M15''' || Toshiba TC74HC132P (×2) || Quad 2-input NAND Schmitt trigger|-| '''M18, M22''' || Toshiba 74HC00AP (×2) || Quad 2-input NAND gate|-| '''M16''' || Toshiba 74HC08AP || Quad 2-input AND gate|-| '''M17''' || Toshiba 74HC14AP || Hex Schmitt-trigger inverter|-| '''M10''' || Seiko S-8054ALR || Voltage detector — power-on reset / low-voltage supervisor|-| '''M21''' || National Semiconductor LM358N || Dual op-amp — analog signal conditioning / comparator|-| '''M20''' || Maxim ICL7660CPA || Switched-capacitor voltage converter — generates the −5 V rail (TP3) from +5 V|-| '''M19''' || Toshiba TDG2002P (TD62002) || 7-channel Darlington sink driver array — drives buzzer / indicators / low-current loads|} === Clock & Configuration === * '''X1''' — 4 MHz crystal (MC6809 ÷4 → 1 MHz E/Q bus clock), with C1/C2 loading trimmers* '''JMP1''' — 3-position configuration jumper* '''BAT1''' — lithium coin cell, backup for the TC5564 SRAM* '''M13''' — unpopulated 8-pin position === Connectors === {| class="wikitable"! Connector !! Function|-| '''J-1''' || +5 V power input to the board|-| '''J-2''' || Front-panel board ([[#OEM No. 126C|OEM No. 126C]]) — LCD display, LED readouts, keypad (40-pin ribbon)|-| '''J-3''' || HV control board ([[#OEM No. 127 (A/B) — HV Controller Board|OEM No. 127]]) — maps pin-for-pin to the 127 board's [[#J-16 Data, Status and Telemetry|J-16]]: DAC setpoint out, voltage/current PWM telemetry in, circuit open/shorted/unknown status|-| '''J-4, J-5''' || Small I/O harnesses (3-pin) — function TBD|} === Other === * '''BZ1''' — muRata piezo buzzer (audible alarm / key-click)* '''Q1–Q5''' transistors, '''D1–D13''' diodes — discrete interface / level shifting* Test points '''TP1–TP7''', '''+5 V''', '''−5 V''' (from ICL7660), '''GND'''* An unpopulated 20-pin DIP position sits between M3 and M11 === Reverse-Engineering Notes === # The MC6809 + MC6821 + dual MC6840 set is a textbook Motorola control core. The two PTMs are well-suited to ''measuring'' the voltage-PWM and current-PWM the 127 board returns over J-3 (gate / capture), and to generating the volt-hour and timed-run intervals for the four operating modes.# J-3 is wired pin-for-pin to the 127 board's J-16, so the 125B PIA directly drives that interface: HV-enable, DAC clock / data / strobe out; circuit open / shorted / unknown status in. The keypad scan / display strobes go to the front panel on J-2.# The Signetics CK2605 FPGA (M7) handles glue logic — address decoding and control sequencing — alongside the discrete 74HC138 / HC00 / HC132 gates.# The S-8054 voltage detector (M10) provides power-on reset and brown-out supervision, gating the CPU and protecting the battery-backed SRAM during power transitions.# The ICL7660 makes a local −5 V rail for the analog / op-amp section rather than relying on the 127 board's ±15 V. === Items Still to Confirm === * Identify the J-4 / J-5 harnesses* Dump the CK2605 (M7) configuration / determine its logic role* Determine J2 pinout to front panel board
==OEM No. 127 (A/B) — HV Controller Board==
