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This is a complex device with a 16 bit CPU, Xilinx 95xx CPLD, Custom Alesis chip (Gate array, PAL, GAL, OTP CPLD?) SRAM, NOR flash 512kb, logic and switching for bus arbitration. BREQ Bus request is a very involved circuit. Also CE# Chip Enable NOR Flash is connected through a complicated muxing circuit.

It has 2 buttons on The Device is quite old school, this was built for the PCB: 1 - RESETearly generation of ADAT/TDIF machines, reset circuit and IC still using physical tape. 2 - Launch monitor diagnostic modeThough tape is not necessary for operation, the sync requirements of locking digital audio, using analogue tape, add a lot of complexity.

It has 2 buttons on the PCB: 1 - RESET, reset circuit and IC 2 - Launch monitor diagnostic mode. A 50 pin header provides easy access to most address lines and relevant (to operation) CPU/RAM/Flash lines. This will be convenient to run a logic capture during boot and operation later.  I beeped out the 50 pin connector - thankfully the vias were not tented - this took absolutely ages as it was : ) <gallery>File:DIFat 50 pin header1 .png|alt=dif at pin header pins 1 - 16|header pins 1 - 16File:DIFat 50 pin header2.png|alt=header pins 16 - 24|header pins 16 - 24File:DIFat 50 pin header3.png|alt=header pins 15 to 38|header pins 15 to 38File:DIFat 50 pin header4.png|alt=header pins 38 to 50|header pins 38 to 50 File:DIFAT PIN HEADER GENERAL NOTES.png|alt=general notes about CPU SRAM, inferred operation|general notes about CPU SRAM, inferred operation</gallery>