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- N
- This edit created a new page (also see list of new pages)
- m
- This is a minor edit
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- This edit was performed by a bot
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28 April 2026
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10:39 | (Upload log) [RSS1 (6×)] | |||
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10:39 RSS1 talk contribs uploaded File:Dif-at-tracerepair4.png (heres the CPU with some 16 traces repaired. Sorry, not a great shot.) | ||||
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10:30 RSS1 talk contribs uploaded File:Dif-at-tracerepair3.png (dif at trace repair place component) | ||||
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10:29 RSS1 talk contribs uploaded File:Dif-at-tracerepair2.png (dif at trace repair tinned fluxed) | ||||
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10:28 RSS1 talk contribs uploaded File:Dif-at-tracerepair.png (dif at trace repair) | ||||
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09:47 RSS1 talk contribs uploaded File:DIF AT RBUS CONNECTOR SCHEMATIC.png | ||||
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08:46 RSS1 talk contribs uploaded File:DIFAT CUTTER SSHOT.png | ||||
27 April 2026
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20:23 | (Upload log) [RSS1 (16×)] | |||
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20:23 RSS1 talk contribs uploaded File:DIF-AT BINVIS.png (DIF AT BINVIS representation.) | ||||
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18:34 RSS1 talk contribs uploaded File:Open OCD.png (OpenOCD reads CPLD) | ||||
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18:33 RSS1 talk contribs uploaded File:Bluetag pin read.png (bluetag determines correct pinout) | ||||
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18:32 RSS1 talk contribs uploaded File:Pullup info.png (pullup info, essential to correct read!) | ||||
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18:31 RSS1 talk contribs uploaded File:XC3SPROG id read.png (XC3SPROG_id_read screenshot.) | ||||
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18:23 RSS1 talk contribs uploaded File:VIVERIS BOUNDARY SCANNER.png | ||||
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16:56 RSS1 talk contribs uploaded File:Xilinx CPLD.jpg (Xilinx CPLD and mux circuit. JTAG pads visible around pin 50 (silkscreen) and 81.) | ||||
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16:53 RSS1 talk contribs uploaded File:Reset circuit.jpg (reset IC and switch) | ||||
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16:49 RSS1 talk contribs uploaded File:5v conditioning circuit.jpeg (power conditioning) | ||||
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16:47 RSS1 talk contribs uploaded File:Sync section optocouplers.JPG (Part of the sync circuitry with optocouplers) | ||||
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13:47 RSS1 talk contribs uploaded File:DIFAT PIN HEADER GENERAL NOTES.png (General notes about the CPU,Flash, SRAM operational pins) | ||||
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12:43 RSS1 talk contribs uploaded File:DIFat 50 pin header4.png (pins 38 -50 on the header) | ||||
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12:41 RSS1 talk contribs uploaded File:DIFat 50 pin header3.png (pins 25 -38 on the header) | ||||
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12:40 RSS1 talk contribs uploaded File:DIFat 50 pin header2.png (pins 16-24 on the header) | ||||
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12:39 RSS1 talk contribs uploaded File:DIFat 50 pin header1 .png (pins 1 to 16 on the header) | ||||
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08:55 RSS1 talk contribs uploaded File:DIF AT FLASH SETTINGS.png | ||||
26 April 2026
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21:40 | (Upload log) [RSS1 (9×)] | |||
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21:40 RSS1 talk contribs uploaded File:DIFAT 24.jpg | ||||
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21:24 RSS1 talk contribs uploaded File:HEW.png (High performance embedded workshop RAM settings for firmware.) | ||||
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21:23 RSS1 talk contribs uploaded File:Binwalk entropy image.png (Binwalk entropy file for firmware) | ||||
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21:22 RSS1 talk contribs uploaded File:H8 3005 CPU.JPG (Roland used a full cpu for this design.) | ||||
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21:20 RSS1 talk contribs uploaded File:Main Board Side On.JPG (main board different angle (missing ICs now)) | ||||
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21:18 RSS1 talk contribs uploaded File:SRAM + NOR FLASH.JPG (Sram and NOR flash chip (512kb)) | ||||
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21:17 RSS1 talk contribs uploaded File:ALESIS OTP CPLD.JPG (Not sure if this is OTP GAL/CPLD. Custom.) | ||||
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21:13 RSS1 talk contribs uploaded File:TDIF-BOARD.JPG (TDIF daughter board.) | ||||
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21:12 RSS1 talk contribs uploaded File:DIF-AT MAIN.JPG (Main board full) | ||||
