Roland DIF-AT: Difference between revisions

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==Device Overview==

This is a complex device with a 16 bit CPU, Xilinx 95xx CPLD, Custom Alesis chip (Gate array, PAL, GAL, OTP CPLD?) SRAM, NOR flash 512kb, logic and switching for bus arbitration. BREQ Bus request is a very involved circuit. Also CE# Chip Enable NOR Flash is connected through a complicated muxing circuit. The Alesis custom IC handles the WE# Write Enable to the NOR Flash, and also seems BREQ master.

This is a complex device with a 16 bit CPU, Xilinx 95xx CPLD, Custom Alesis chip (ASIC, Gate array, PAL, GAL, OTP CPLD?) SRAM, NOR flash 512kb, logic and switching for bus arbitration. BREQ Bus request is a very involved circuit. Also CE# Chip Enable NOR Flash is connected through a complicated muxing circuit. The Alesis custom IC handles the WE# Write Enable to the NOR Flash, and also seems BREQ master.

No info could be found on the Alesis chip, searching for the numerous IC markings revealed nothing.

No info could be found on the Alesis chip, searching for the numerous IC markings revealed nothing. After more research, it seems likely it is an ASIC, as the functions it performs are advanced.

The Device is quite old school. This was built for the early generation of ADAT/TDIF machines, still using physical tape. Thankfully a tape machine is not necessary for operation. The sync requirements of locking digital audio using analogue tape definitely adds complexity to this system.

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This device has two firmware version strings visible in the firmware (at this point the strings are the only thing I've been able to see)

Appears it was already updated in the field to the last OS version (1.022) from I'm not sure if it then wipes the other bank? Possibly, because the other regions are written with FF. However it was still pretty confusing to navigate around later on; BRA from active code to 0xFF region. I'm still not sure: maybe the Alesis ~~CPLD~~ remaps certain memory addresses at run time? I've added peripheral mapping for the SCI, still it's tricky to find things with little experience. I am learning a lot though.

Appears it was already updated in the field to the last OS version (1.022) from I'm not sure if it then wipes the other bank? Possibly, because the other regions are written with FF. However it was still pretty confusing to navigate around later on; BRA from active code to 0xFF region. I'm still not sure: maybe the Alesis ASIC remaps certain memory addresses at run time? (more research has shown that this is very likely) I've added peripheral mapping for the SCI, still it's tricky to find things with little experience. I am learning a lot though.

[[File:Binwalk entropy image.png|left|thumb|Binwalk entropy image looking good - encouraging at least]]

[[File:DIF-AT BINVIS.png|alt=binvis.io|center|thumb|BINVIS The little 'white line defined' area is where the pointer is viewing]]

@@ Line 41: / Line 41: @@
 ==Device Overview==
-This is a complex device with a 16 bit CPU, Xilinx 95xx CPLD, Custom Alesis chip (Gate array, PAL, GAL, OTP CPLD?) SRAM, NOR flash 512kb, logic and switching for bus arbitration.  BREQ Bus request is a very involved circuit.  Also CE# Chip Enable NOR Flash is connected through a complicated muxing circuit.  The Alesis custom IC handles the WE# Write Enable to the NOR Flash, and also seems BREQ master.
+This is a complex device with a 16 bit CPU, Xilinx 95xx CPLD, Custom Alesis chip (ASIC, Gate array, PAL, GAL, OTP CPLD?) SRAM, NOR flash 512kb, logic and switching for bus arbitration.  BREQ Bus request is a very involved circuit.  Also CE# Chip Enable NOR Flash is connected through a complicated muxing circuit.  The Alesis custom IC handles the WE# Write Enable to the NOR Flash, and also seems BREQ master.
-No info could be found on the Alesis chip, searching for the numerous IC markings revealed nothing.
+No info could be found on the Alesis chip, searching for the numerous IC markings revealed nothing.  After more research, it seems likely it is an ASIC, as the functions it performs are advanced.
 The Device is quite old school.  This was built for the early generation of ADAT/TDIF machines, still using physical tape.  Thankfully a tape machine is not necessary for operation.  The sync requirements of locking digital audio using analogue tape definitely adds complexity to this system.
@@ Line 145: / Line 145: @@
 This device has two firmware version strings visible in the firmware (at this point the strings are the only thing I've been able to see)
-Appears it was already updated in the field to the last OS version (1.022) from  I'm not sure if it then wipes the other bank?  Possibly, because the other regions are written with FF.  However it was still pretty confusing to navigate around later on; BRA from active code to 0xFF region.  I'm still not sure: maybe the Alesis CPLD remaps certain memory addresses at run time?  I've added peripheral mapping for the SCI, still it's tricky to find things with little experience.  I am learning a lot though.
+Appears it was already updated in the field to the last OS version (1.022) from  I'm not sure if it then wipes the other bank?  Possibly, because the other regions are written with FF.  However it was still pretty confusing to navigate around later on; BRA from active code to 0xFF region.  I'm still not sure: maybe the Alesis ASIC remaps certain memory addresses at run time?  (more research has shown that this is very likely)  I've added peripheral mapping for the SCI, still it's tricky to find things with little experience.  I am learning a lot though.
 [[File:Binwalk entropy image.png|left|thumb|Binwalk entropy image looking good - encouraging at least]]
 [[File:DIF-AT BINVIS.png|alt=binvis.io|center|thumb|BINVIS The little 'white line defined' area is where the pointer is viewing]]