38
edits
Changes
Add instruction cycle timing notes
*[https://web.archive.org/web/20200914132431/https://www.st.com/resource/en/programming_manual/cd00004617-st7-family-icc-protocol-reference-manual-stmicroelectronics.pdf ST7 Family ICC Protocol Reference Manual]
*With a buffered 16MHz clock provided by Y3/U12, possible CPU speeds are 16MHz, 8MHz(/2), 4MHz(/4), 2MHz(/8) depending on MCC configuration.
*Instruction timings have yet to be found. The datasheet only says '2-12 cycles per instruction', and a note from Raisonance support says that NOP does indeed take 2 cycles. These will be needed before we can bring up a bit-banged software debug UART as well as the bitstream for the CC1050, and may need to be reverse engineered via GPIO+oscilloscope.
''U4 - (Marked Z252)''